cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dm8148-t410.dts (2575B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/dts-v1/;
      3
      4#include "dm814x.dtsi"
      5
      6/ {
      7	model = "HP t410 Smart Zero Client";
      8	compatible = "hp,t410", "ti,dm8148", "ti,dm814";
      9
     10	memory@80000000 {
     11		device_type = "memory";
     12		reg = <0x80000000 0x40000000>;	/* 1 GB */
     13	};
     14
     15	/* gpio9 seems to control USB VBUS regulator and/or hub power */
     16	usb_power: regulator@9 {
     17		compatible = "regulator-fixed";
     18		regulator-name = "usb_power";
     19		regulator-min-microvolt = <5000000>;
     20		regulator-max-microvolt = <5000000>;
     21		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
     22		enable-active-high;
     23		regulator-always-on;
     24	};
     25
     26	vmmcsd_fixed: fixedregulator0 {
     27		compatible = "regulator-fixed";
     28		regulator-name = "vmmcsd_fixed";
     29		regulator-min-microvolt = <3300000>;
     30		regulator-max-microvolt = <3300000>;
     31	};
     32};
     33
     34&cpsw_emac0 {
     35	phy-handle = <&ethphy0>;
     36	phy-mode = "rgmii-id";
     37};
     38
     39&cpsw_emac1 {
     40	phy-handle = <&ethphy1>;
     41	phy-mode = "rgmii-id";
     42};
     43
     44&davinci_mdio {
     45	ethphy0: ethernet-phy@0 {
     46		reg = <0>;
     47	};
     48
     49	ethphy1: ethernet-phy@1 {
     50		reg = <1>;
     51	};
     52};
     53
     54&mmc1 {
     55	status = "disabled";
     56};
     57
     58&mmc2 {
     59	status = "disabled";
     60};
     61
     62&mmc3 {
     63	pinctrl-names = "default";
     64	pinctrl-0 = <&sd2_pins>;
     65	vmmc-supply = <&vmmcsd_fixed>;
     66	bus-width = <8>;
     67	dmas = <&edma_xbar 8 0 1	/* use SDTXEVT1 instead of MCASP0TX */
     68		&edma_xbar 9 0 2>;	/* use SDRXEVT1 instead of MCASP0RX */
     69	dma-names = "tx", "rx";
     70	non-removable;
     71};
     72
     73&pincntl {
     74	sd2_pins: pinmux_sd2_pins {
     75		pinctrl-single,pins = <
     76			DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[7] */
     77			DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[6] */
     78			DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[5] */
     79			DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[4] */
     80			DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[3] */
     81			DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[2] */
     82			DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[1] */
     83			DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[0] */
     84			DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1)		/* SD2_CLK */
     85			DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2)	/* SD2_CMD */
     86			DM814X_IOPAD(0x0920, PIN_INPUT | 0x40)	/* SD2_SDCD */
     87			>;
     88	};
     89
     90	usb0_pins: pinmux_usb0_pins {
     91		pinctrl-single,pins = <
     92			DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)	/* USB0_DRVVBUS */
     93			>;
     94	};
     95
     96	usb1_pins: pinmux_usb1_pins {
     97		pinctrl-single,pins = <
     98			DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80)	/* USB1_DRVVBUS */
     99			>;
    100	};
    101};
    102
    103&usb0 {
    104	pinctrl-names = "default";
    105	pinctrl-0 = <&usb0_pins>;
    106	dr_mode = "host";
    107};
    108
    109&usb1 {
    110	pinctrl-names = "default";
    111	pinctrl-0 = <&usb1_pins>;
    112	dr_mode = "host";
    113};