dm816x.dtsi (17002B)
1/* 2 * This file is licensed under the terms of the GNU General Public License 3 * version 2. This program is licensed "as is" without any warranty of any 4 * kind, whether express or implied. 5 */ 6 7#include <dt-bindings/bus/ti-sysc.h> 8#include <dt-bindings/clock/dm816.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/omap.h> 11 12/ { 13 compatible = "ti,dm816"; 14 interrupt-parent = <&intc>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 chosen { }; 18 19 aliases { 20 i2c0 = &i2c1; 21 i2c1 = &i2c2; 22 serial0 = &uart1; 23 serial1 = &uart2; 24 serial2 = &uart3; 25 ethernet0 = ð0; 26 ethernet1 = ð1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 cpu@0 { 33 compatible = "arm,cortex-a8"; 34 device_type = "cpu"; 35 reg = <0>; 36 }; 37 }; 38 39 pmu { 40 compatible = "arm,cortex-a8-pmu"; 41 interrupts = <3>; 42 }; 43 44 /* 45 * The soc node represents the soc top level view. It is used for IPs 46 * that are not memory mapped in the MPU view or for the MPU itself. 47 */ 48 soc { 49 compatible = "ti,omap-infra"; 50 mpu { 51 compatible = "ti,omap3-mpu"; 52 ti,hwmods = "mpu"; 53 }; 54 }; 55 56 /* 57 * XXX: Use a flat representation of the dm816x interconnect. 58 * The real dm816x interconnect network is quite complex. Since 59 * it will not bring real advantage to represent that in DT 60 * for the moment, just use a fake OCP bus entry to represent 61 * the whole bus hierarchy. 62 */ 63 ocp { 64 compatible = "simple-bus"; 65 reg = <0x44000000 0x10000>; 66 interrupts = <9 10>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 prcm: prcm@48180000 { 72 compatible = "ti,dm816-prcm", "simple-bus"; 73 reg = <0x48180000 0x4000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0 0x48180000 0x4000>; 77 78 prcm_clocks: clocks { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 }; 82 83 prcm_clockdomains: clockdomains { 84 }; 85 }; 86 87 scrm: scrm@48140000 { 88 compatible = "ti,dm816-scrm", "simple-bus"; 89 reg = <0x48140000 0x21000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 #pinctrl-cells = <1>; 93 ranges = <0 0x48140000 0x21000>; 94 95 dm816x_pinmux: pinmux@800 { 96 compatible = "pinctrl-single"; 97 reg = <0x800 0x50a>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <16>; 102 pinctrl-single,function-mask = <0xf>; 103 }; 104 105 /* Device Configuration Registers */ 106 scm_conf: syscon@600 { 107 compatible = "syscon", "simple-bus"; 108 reg = <0x600 0x110>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0x600 0x110>; 112 113 usb_phy0: usb-phy@20 { 114 compatible = "ti,dm8168-usb-phy"; 115 reg = <0x20 0x8>; 116 reg-names = "phy"; 117 clocks = <&main_fapll 6>; 118 clock-names = "refclk"; 119 #phy-cells = <0>; 120 syscon = <&scm_conf>; 121 }; 122 123 usb_phy1: usb-phy@28 { 124 compatible = "ti,dm8168-usb-phy"; 125 reg = <0x28 0x8>; 126 reg-names = "phy"; 127 clocks = <&main_fapll 6>; 128 clock-names = "refclk"; 129 #phy-cells = <0>; 130 syscon = <&scm_conf>; 131 }; 132 }; 133 134 scrm_clocks: clocks { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 }; 138 139 scrm_clockdomains: clockdomains { 140 }; 141 }; 142 143 target-module@49000000 { 144 compatible = "ti,sysc-omap4", "ti,sysc"; 145 reg = <0x49000000 0x4>; 146 reg-names = "rev"; 147 clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; 148 clock-names = "fck"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x49000000 0x10000>; 152 153 edma: dma@0 { 154 compatible = "ti,edma3-tpcc"; 155 reg = <0 0x10000>; 156 reg-names = "edma3_cc"; 157 interrupts = <12 13 14>; 158 interrupt-names = "edma3_ccint", "edma3_mperr", 159 "edma3_ccerrint"; 160 dma-requests = <64>; 161 #dma-cells = <2>; 162 163 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 164 <&edma_tptc2 3>, <&edma_tptc3 0>; 165 166 ti,edma-memcpy-channels = <20 21>; 167 }; 168 }; 169 170 target-module@49800000 { 171 compatible = "ti,sysc-omap4", "ti,sysc"; 172 reg = <0x49800000 0x4>, 173 <0x49800010 0x4>; 174 reg-names = "rev", "sysc"; 175 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 176 ti,sysc-midle = <SYSC_IDLE_FORCE>; 177 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 178 <SYSC_IDLE_SMART>; 179 clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; 180 clock-names = "fck"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0x0 0x49800000 0x100000>; 184 185 edma_tptc0: dma@0 { 186 compatible = "ti,edma3-tptc"; 187 reg = <0 0x100000>; 188 interrupts = <112>; 189 interrupt-names = "edma3_tcerrint"; 190 }; 191 }; 192 193 target-module@49900000 { 194 compatible = "ti,sysc-omap4", "ti,sysc"; 195 reg = <0x49900000 0x4>, 196 <0x49900010 0x4>; 197 reg-names = "rev", "sysc"; 198 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 199 ti,sysc-midle = <SYSC_IDLE_FORCE>; 200 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 201 <SYSC_IDLE_SMART>; 202 clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; 203 clock-names = "fck"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0x0 0x49900000 0x100000>; 207 208 edma_tptc1: dma@0 { 209 compatible = "ti,edma3-tptc"; 210 reg = <0 0x100000>; 211 interrupts = <113>; 212 interrupt-names = "edma3_tcerrint"; 213 }; 214 }; 215 216 target-module@49a00000 { 217 compatible = "ti,sysc-omap4", "ti,sysc"; 218 reg = <0x49a00000 0x4>, 219 <0x49a00010 0x4>; 220 reg-names = "rev", "sysc"; 221 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 222 ti,sysc-midle = <SYSC_IDLE_FORCE>; 223 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224 <SYSC_IDLE_SMART>; 225 clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; 226 clock-names = "fck"; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0x0 0x49a00000 0x100000>; 230 231 edma_tptc2: dma@0 { 232 compatible = "ti,edma3-tptc"; 233 reg = <0 0x100000>; 234 interrupts = <114>; 235 interrupt-names = "edma3_tcerrint"; 236 }; 237 }; 238 239 target-module@49b00000 { 240 compatible = "ti,sysc-omap4", "ti,sysc"; 241 reg = <0x49b00000 0x4>, 242 <0x49b00010 0x4>; 243 reg-names = "rev", "sysc"; 244 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 245 ti,sysc-midle = <SYSC_IDLE_FORCE>; 246 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 247 <SYSC_IDLE_SMART>; 248 clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; 249 clock-names = "fck"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges = <0x0 0x49b00000 0x100000>; 253 254 edma_tptc3: dma@0 { 255 compatible = "ti,edma3-tptc"; 256 reg = <0 0x100000>; 257 interrupts = <115>; 258 interrupt-names = "edma3_tcerrint"; 259 }; 260 }; 261 262 elm: elm@48080000 { 263 compatible = "ti,am3352-elm"; 264 ti,hwmods = "elm"; 265 reg = <0x48080000 0x2000>; 266 interrupts = <4>; 267 }; 268 269 gpio1: gpio@48032000 { 270 compatible = "ti,omap4-gpio"; 271 ti,hwmods = "gpio1"; 272 ti,gpio-always-on; 273 reg = <0x48032000 0x1000>; 274 interrupts = <96>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 }; 280 281 gpio2: gpio@4804c000 { 282 compatible = "ti,omap4-gpio"; 283 ti,hwmods = "gpio2"; 284 ti,gpio-always-on; 285 reg = <0x4804c000 0x1000>; 286 interrupts = <98>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 293 gpmc: gpmc@50000000 { 294 compatible = "ti,am3352-gpmc"; 295 ti,hwmods = "gpmc"; 296 reg = <0x50000000 0x2000>; 297 #address-cells = <2>; 298 #size-cells = <1>; 299 interrupts = <100>; 300 dmas = <&edma 52 0>; 301 dma-names = "rxtx"; 302 gpmc,num-cs = <6>; 303 gpmc,num-waitpins = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 }; 309 310 i2c1: i2c@48028000 { 311 compatible = "ti,omap4-i2c"; 312 ti,hwmods = "i2c1"; 313 reg = <0x48028000 0x1000>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 interrupts = <70>; 317 }; 318 319 i2c2: i2c@4802a000 { 320 compatible = "ti,omap4-i2c"; 321 ti,hwmods = "i2c2"; 322 reg = <0x4802a000 0x1000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 interrupts = <71>; 326 }; 327 328 intc: interrupt-controller@48200000 { 329 compatible = "ti,dm816-intc"; 330 interrupt-controller; 331 #interrupt-cells = <1>; 332 reg = <0x48200000 0x1000>; 333 }; 334 335 rtc: rtc@480c0000 { 336 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 337 reg = <0x480c0000 0x1000>; 338 interrupts = <75 76>; 339 ti,hwmods = "rtc"; 340 }; 341 342 mailbox: mailbox@480c8000 { 343 compatible = "ti,omap4-mailbox"; 344 reg = <0x480c8000 0x2000>; 345 interrupts = <77>; 346 ti,hwmods = "mailbox"; 347 #mbox-cells = <1>; 348 ti,mbox-num-users = <4>; 349 ti,mbox-num-fifos = <12>; 350 mbox_dsp: mbox-dsp { 351 ti,mbox-tx = <3 0 0>; 352 ti,mbox-rx = <0 0 0>; 353 }; 354 }; 355 356 spinbox: spinbox@480ca000 { 357 compatible = "ti,omap4-hwspinlock"; 358 reg = <0x480ca000 0x2000>; 359 ti,hwmods = "spinbox"; 360 #hwlock-cells = <1>; 361 }; 362 363 mdio: mdio@4a100800 { 364 compatible = "ti,davinci_mdio"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <0x4a100800 0x100>; 368 ti,hwmods = "davinci_mdio"; 369 bus_freq = <1000000>; 370 phy0: ethernet-phy@0 { 371 reg = <1>; 372 }; 373 phy1: ethernet-phy@1 { 374 reg = <2>; 375 }; 376 }; 377 378 eth0: ethernet@4a100000 { 379 compatible = "ti,dm816-emac"; 380 ti,hwmods = "emac0"; 381 reg = <0x4a100000 0x800 382 0x4a100900 0x3700>; 383 clocks = <&sysclk24_ck>; 384 syscon = <&scm_conf>; 385 ti,davinci-ctrl-reg-offset = <0>; 386 ti,davinci-ctrl-mod-reg-offset = <0x900>; 387 ti,davinci-ctrl-ram-offset = <0x2000>; 388 ti,davinci-ctrl-ram-size = <0x2000>; 389 interrupts = <40 41 42 43>; 390 phy-handle = <&phy0>; 391 }; 392 393 eth1: ethernet@4a120000 { 394 compatible = "ti,dm816-emac"; 395 ti,hwmods = "emac1"; 396 reg = <0x4a120000 0x4000>; 397 clocks = <&sysclk24_ck>; 398 syscon = <&scm_conf>; 399 ti,davinci-ctrl-reg-offset = <0>; 400 ti,davinci-ctrl-mod-reg-offset = <0x900>; 401 ti,davinci-ctrl-ram-offset = <0x2000>; 402 ti,davinci-ctrl-ram-size = <0x2000>; 403 interrupts = <44 45 46 47>; 404 phy-handle = <&phy1>; 405 }; 406 407 sata: sata@4a140000 { 408 compatible = "ti,dm816-ahci"; 409 reg = <0x4a140000 0x10000>; 410 interrupts = <16>; 411 ti,hwmods = "sata"; 412 }; 413 414 mcspi1: spi@48030000 { 415 compatible = "ti,omap4-mcspi"; 416 reg = <0x48030000 0x1000>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 interrupts = <65>; 420 ti,spi-num-cs = <4>; 421 ti,hwmods = "mcspi1"; 422 dmas = <&edma 16 0 &edma 17 0 423 &edma 18 0 &edma 19 0 424 &edma 20 0 &edma 21 0 425 &edma 22 0 &edma 23 0>; 426 dma-names = "tx0", "rx0", "tx1", "rx1", 427 "tx2", "rx2", "tx3", "rx3"; 428 }; 429 430 mmc1: mmc@48060000 { 431 compatible = "ti,omap4-hsmmc"; 432 reg = <0x48060000 0x11000>; 433 ti,hwmods = "mmc1"; 434 interrupts = <64>; 435 dmas = <&edma 24 0 &edma 25 0>; 436 dma-names = "tx", "rx"; 437 }; 438 439 timer1_target: target-module@4802e000 { 440 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 441 reg = <0x4802e000 0x4>, 442 <0x4802e010 0x4>; 443 reg-names = "rev", "sysc"; 444 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 445 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 446 <SYSC_IDLE_NO>, 447 <SYSC_IDLE_SMART>, 448 <SYSC_IDLE_SMART_WKUP>; 449 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; 450 clock-names = "fck"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges = <0x0 0x4802e000 0x1000>; 454 455 timer1: timer@0 { 456 compatible = "ti,dm816-timer"; 457 reg = <0 0x1000>; 458 interrupts = <67>; 459 ti,timer-alwon; 460 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; 461 clock-names = "fck"; 462 }; 463 }; 464 465 timer2_target: target-module@48040000 { 466 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 467 reg = <0x48040000 0x4>, 468 <0x48040010 0x4>; 469 reg-names = "rev", "sysc"; 470 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 471 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 472 <SYSC_IDLE_NO>, 473 <SYSC_IDLE_SMART>, 474 <SYSC_IDLE_SMART_WKUP>; 475 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; 476 clock-names = "fck"; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 ranges = <0x0 0x48040000 0x1000>; 480 481 timer2: timer@0 { 482 compatible = "ti,dm816-timer"; 483 reg = <0 0x1000>; 484 interrupts = <68>; 485 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; 486 clock-names = "fck"; 487 }; 488 }; 489 490 timer3: timer@48042000 { 491 compatible = "ti,dm816-timer"; 492 reg = <0x48042000 0x2000>; 493 interrupts = <69>; 494 ti,hwmods = "timer3"; 495 }; 496 497 timer4: timer@48044000 { 498 compatible = "ti,dm816-timer"; 499 reg = <0x48044000 0x2000>; 500 interrupts = <92>; 501 ti,hwmods = "timer4"; 502 ti,timer-pwm; 503 }; 504 505 timer5: timer@48046000 { 506 compatible = "ti,dm816-timer"; 507 reg = <0x48046000 0x2000>; 508 interrupts = <93>; 509 ti,hwmods = "timer5"; 510 ti,timer-pwm; 511 }; 512 513 timer6: timer@48048000 { 514 compatible = "ti,dm816-timer"; 515 reg = <0x48048000 0x2000>; 516 interrupts = <94>; 517 ti,hwmods = "timer6"; 518 ti,timer-pwm; 519 }; 520 521 timer7: timer@4804a000 { 522 compatible = "ti,dm816-timer"; 523 reg = <0x4804a000 0x2000>; 524 interrupts = <95>; 525 ti,hwmods = "timer7"; 526 ti,timer-pwm; 527 }; 528 529 uart1: uart@48020000 { 530 compatible = "ti,am3352-uart", "ti,omap3-uart"; 531 ti,hwmods = "uart1"; 532 reg = <0x48020000 0x2000>; 533 clock-frequency = <48000000>; 534 interrupts = <72>; 535 dmas = <&edma 26 0 &edma 27 0>; 536 dma-names = "tx", "rx"; 537 }; 538 539 uart2: uart@48022000 { 540 compatible = "ti,am3352-uart", "ti,omap3-uart"; 541 ti,hwmods = "uart2"; 542 reg = <0x48022000 0x2000>; 543 clock-frequency = <48000000>; 544 interrupts = <73>; 545 dmas = <&edma 28 0 &edma 29 0>; 546 dma-names = "tx", "rx"; 547 }; 548 549 uart3: uart@48024000 { 550 compatible = "ti,am3352-uart", "ti,omap3-uart"; 551 ti,hwmods = "uart3"; 552 reg = <0x48024000 0x2000>; 553 clock-frequency = <48000000>; 554 interrupts = <74>; 555 dmas = <&edma 30 0 &edma 31 0>; 556 dma-names = "tx", "rx"; 557 }; 558 559 /* NOTE: USB needs a transceiver driver for phys to work */ 560 usb: usb_otg_hs@47401000 { 561 compatible = "ti,am33xx-usb"; 562 reg = <0x47401000 0x400000>; 563 ranges; 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ti,hwmods = "usb_otg_hs"; 567 568 usb0: usb@47401000 { 569 compatible = "ti,musb-dm816"; 570 reg = <0x47401400 0x400 571 0x47401000 0x200>; 572 reg-names = "mc", "control"; 573 interrupts = <18>; 574 interrupt-names = "mc"; 575 dr_mode = "host"; 576 interface-type = <0>; 577 phys = <&usb_phy0>; 578 phy-names = "usb2-phy"; 579 mentor,multipoint = <1>; 580 mentor,num-eps = <16>; 581 mentor,ram-bits = <12>; 582 mentor,power = <500>; 583 584 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 585 &cppi41dma 2 0 &cppi41dma 3 0 586 &cppi41dma 4 0 &cppi41dma 5 0 587 &cppi41dma 6 0 &cppi41dma 7 0 588 &cppi41dma 8 0 &cppi41dma 9 0 589 &cppi41dma 10 0 &cppi41dma 11 0 590 &cppi41dma 12 0 &cppi41dma 13 0 591 &cppi41dma 14 0 &cppi41dma 0 1 592 &cppi41dma 1 1 &cppi41dma 2 1 593 &cppi41dma 3 1 &cppi41dma 4 1 594 &cppi41dma 5 1 &cppi41dma 6 1 595 &cppi41dma 7 1 &cppi41dma 8 1 596 &cppi41dma 9 1 &cppi41dma 10 1 597 &cppi41dma 11 1 &cppi41dma 12 1 598 &cppi41dma 13 1 &cppi41dma 14 1>; 599 dma-names = 600 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 601 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 602 "rx14", "rx15", 603 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 604 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 605 "tx14", "tx15"; 606 }; 607 608 usb1: usb@47401800 { 609 compatible = "ti,musb-dm816"; 610 reg = <0x47401c00 0x400 611 0x47401800 0x200>; 612 reg-names = "mc", "control"; 613 interrupts = <19>; 614 interrupt-names = "mc"; 615 dr_mode = "host"; 616 interface-type = <0>; 617 phys = <&usb_phy1>; 618 phy-names = "usb2-phy"; 619 mentor,multipoint = <1>; 620 mentor,num-eps = <16>; 621 mentor,ram-bits = <12>; 622 mentor,power = <500>; 623 624 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 625 &cppi41dma 17 0 &cppi41dma 18 0 626 &cppi41dma 19 0 &cppi41dma 20 0 627 &cppi41dma 21 0 &cppi41dma 22 0 628 &cppi41dma 23 0 &cppi41dma 24 0 629 &cppi41dma 25 0 &cppi41dma 26 0 630 &cppi41dma 27 0 &cppi41dma 28 0 631 &cppi41dma 29 0 &cppi41dma 15 1 632 &cppi41dma 16 1 &cppi41dma 17 1 633 &cppi41dma 18 1 &cppi41dma 19 1 634 &cppi41dma 20 1 &cppi41dma 21 1 635 &cppi41dma 22 1 &cppi41dma 23 1 636 &cppi41dma 24 1 &cppi41dma 25 1 637 &cppi41dma 26 1 &cppi41dma 27 1 638 &cppi41dma 28 1 &cppi41dma 29 1>; 639 dma-names = 640 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 641 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 642 "rx14", "rx15", 643 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 644 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 645 "tx14", "tx15"; 646 }; 647 648 cppi41dma: dma-controller@47402000 { 649 compatible = "ti,am3359-cppi41"; 650 reg = <0x47400000 0x1000 651 0x47402000 0x1000 652 0x47403000 0x1000 653 0x47404000 0x4000>; 654 reg-names = "glue", "controller", "scheduler", "queuemgr"; 655 interrupts = <17>; 656 interrupt-names = "glue"; 657 #dma-cells = <2>; 658 /* For backwards compatibility: */ 659 #dma-channels = <30>; 660 dma-channels = <30>; 661 #dma-requests = <256>; 662 dma-requests = <256>; 663 }; 664 }; 665 666 wd_timer2: wd_timer@480c2000 { 667 compatible = "ti,omap3-wdt"; 668 ti,hwmods = "wd_timer"; 669 reg = <0x480c2000 0x1000>; 670 interrupts = <0>; 671 }; 672 }; 673}; 674 675#include "dm816x-clocks.dtsi" 676 677/* Preferred always-on timer for clocksource */ 678&timer1_target { 679 ti,no-reset-on-init; 680 ti,no-idle; 681 timer@0 { 682 assigned-clocks = <&timer1_fck>; 683 assigned-clock-parents = <&sys_clkin_ck>; 684 }; 685}; 686 687/* Preferred timer for clockevent */ 688&timer2_target { 689 ti,no-reset-on-init; 690 ti,no-idle; 691 timer@0 { 692 assigned-clocks = <&timer2_fck>; 693 assigned-clock-parents = <&sys_clkin_ck>; 694 }; 695};