cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dove-cubox.dts (2561B)

      1// SPDX-License-Identifier: GPL-2.0
      2/dts-v1/;
      3
      4#include "dove.dtsi"
      5
      6/ {
      7	model = "SolidRun CuBox";
      8	compatible = "solidrun,cubox", "marvell,dove";
      9
     10	memory {
     11		device_type = "memory";
     12		reg = <0x00000000 0x40000000>;
     13	};
     14
     15	chosen {
     16		bootargs = "console=ttyS0,115200n8 earlyprintk";
     17	};
     18
     19	leds {
     20		compatible = "gpio-leds";
     21		pinctrl-0 = <&pmx_gpio_18>;
     22		pinctrl-names = "default";
     23
     24		power {
     25			label = "Power";
     26			gpios = <&gpio0 18 1>;
     27			default-state = "keep";
     28		};
     29	};
     30
     31	regulators {
     32		compatible = "simple-bus";
     33		#address-cells = <1>;
     34		#size-cells = <0>;
     35
     36		usb_power: regulator@1 {
     37			compatible = "regulator-fixed";
     38			reg = <1>;
     39			regulator-name = "USB Power";
     40			regulator-min-microvolt = <5000000>;
     41			regulator-max-microvolt = <5000000>;
     42			enable-active-high;
     43			regulator-always-on;
     44			regulator-boot-on;
     45			gpio = <&gpio0 1 0>;
     46			pinctrl-0 = <&pmx_gpio_1>;
     47			pinctrl-names = "default";
     48		};
     49	};
     50
     51	clocks {
     52		/* 25MHz reference crystal */
     53		ref25: oscillator {
     54			compatible = "fixed-clock";
     55			#clock-cells = <0>;
     56			clock-frequency = <25000000>;
     57		};
     58	};
     59
     60	ir_recv: ir-receiver {
     61		compatible = "gpio-ir-receiver";
     62		gpios = <&gpio0 19 1>;
     63		pinctrl-0 = <&pmx_gpio_19>;
     64		pinctrl-names = "default";
     65	};
     66
     67	gpu-subsystem {
     68		status = "okay";
     69	};
     70};
     71
     72&uart0 { status = "okay"; };
     73&sata0 { status = "okay"; };
     74&mdio { status = "okay"; };
     75&eth { status = "okay"; };
     76
     77&ethphy {
     78	compatible = "marvell,88e1310";
     79	reg = <1>;
     80};
     81
     82&gpu {
     83	status = "okay";
     84};
     85
     86&i2c0 {
     87	status = "okay";
     88	clock-frequency = <100000>;
     89
     90	si5351: clock-generator@60 {
     91		compatible = "silabs,si5351a-msop";
     92		reg = <0x60>;
     93		#address-cells = <1>;
     94		#size-cells = <0>;
     95		#clock-cells = <1>;
     96
     97		/* connect xtal input to 25MHz reference */
     98		clocks = <&ref25>;
     99		clock-names = "xtal";
    100
    101		/* connect xtal input as source of pll0 and pll1 */
    102		silabs,pll-source = <0 0>, <1 0>;
    103
    104		clkout0 {
    105			reg = <0>;
    106			silabs,drive-strength = <8>;
    107			silabs,multisynth-source = <0>;
    108			silabs,clock-source = <0>;
    109			silabs,pll-master;
    110		};
    111
    112		clkout2 {
    113			reg = <2>;
    114			silabs,drive-strength = <8>;
    115			silabs,multisynth-source = <1>;
    116			silabs,clock-source = <0>;
    117			silabs,pll-master;
    118		};
    119	};
    120};
    121
    122&sdio0 {
    123	status = "okay";
    124};
    125
    126&spi0 {
    127	status = "okay";
    128
    129	/* spi0.0: 4M Flash Winbond W25Q32BV */
    130	flash@0 {
    131		compatible = "st,w25q32";
    132		spi-max-frequency = <20000000>;
    133		reg = <0>;
    134	};
    135};
    136
    137&audio1 {
    138	status = "okay";
    139	clocks = <&gate_clk 13>, <&si5351 2>;
    140	clock-names = "internal", "extclk";
    141	pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>;
    142	pinctrl-names = "default";
    143};