cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dra74x.dtsi (5468B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
      4 *
      5 * Based on "omap4.dtsi"
      6 */
      7
      8#include "dra7.dtsi"
      9
     10/ {
     11	compatible = "ti,dra742", "ti,dra74", "ti,dra7";
     12
     13	cpus {
     14		cpu@1 {
     15			device_type = "cpu";
     16			compatible = "arm,cortex-a15";
     17			reg = <1>;
     18			operating-points-v2 = <&cpu0_opp_table>;
     19
     20			clocks = <&dpll_mpu_ck>;
     21			clock-names = "cpu";
     22
     23			clock-latency = <300000>; /* From omap-cpufreq driver */
     24
     25			/* cooling options */
     26			#cooling-cells = <2>; /* min followed by max */
     27
     28			vbb-supply = <&abb_mpu>;
     29		};
     30	};
     31
     32	aliases {
     33		rproc0 = &ipu1;
     34		rproc1 = &ipu2;
     35		rproc2 = &dsp1;
     36		rproc3 = &dsp2;
     37	};
     38
     39	pmu {
     40		compatible = "arm,cortex-a15-pmu";
     41		interrupt-parent = <&wakeupgen>;
     42		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
     43			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
     44	};
     45
     46	ocp {
     47		dsp2_system: dsp_system@41500000 {
     48			compatible = "syscon";
     49			reg = <0x41500000 0x100>;
     50		};
     51
     52
     53		target-module@41501000 {
     54			compatible = "ti,sysc-omap2", "ti,sysc";
     55			reg = <0x41501000 0x4>,
     56			      <0x41501010 0x4>,
     57			      <0x41501014 0x4>;
     58			reg-names = "rev", "sysc", "syss";
     59			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     60					<SYSC_IDLE_NO>,
     61					<SYSC_IDLE_SMART>;
     62			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
     63					 SYSC_OMAP2_SOFTRESET |
     64					 SYSC_OMAP2_AUTOIDLE)>;
     65			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
     66			clock-names = "fck";
     67			resets = <&prm_dsp2 1>;
     68			reset-names = "rstctrl";
     69			ranges = <0x0 0x41501000 0x1000>;
     70			#size-cells = <1>;
     71			#address-cells = <1>;
     72
     73			mmu0_dsp2: mmu@0 {
     74				compatible = "ti,dra7-dsp-iommu";
     75				reg = <0x0 0x100>;
     76				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
     77				#iommu-cells = <0>;
     78				ti,syscon-mmuconfig = <&dsp2_system 0x0>;
     79			};
     80		};
     81
     82		target-module@41502000 {
     83			compatible = "ti,sysc-omap2", "ti,sysc";
     84			reg = <0x41502000 0x4>,
     85			      <0x41502010 0x4>,
     86			      <0x41502014 0x4>;
     87			reg-names = "rev", "sysc", "syss";
     88			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     89					<SYSC_IDLE_NO>,
     90					<SYSC_IDLE_SMART>;
     91			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
     92					 SYSC_OMAP2_SOFTRESET |
     93					 SYSC_OMAP2_AUTOIDLE)>;
     94
     95			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
     96			clock-names = "fck";
     97			resets = <&prm_dsp2 1>;
     98			reset-names = "rstctrl";
     99			ranges = <0x0 0x41502000 0x1000>;
    100			#size-cells = <1>;
    101			#address-cells = <1>;
    102
    103			mmu1_dsp2: mmu@0 {
    104				compatible = "ti,dra7-dsp-iommu";
    105				reg = <0x0 0x100>;
    106				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
    107				#iommu-cells = <0>;
    108				ti,syscon-mmuconfig = <&dsp2_system 0x1>;
    109			};
    110		};
    111
    112		dsp2: dsp@41000000 {
    113			compatible = "ti,dra7-dsp";
    114			reg = <0x41000000 0x48000>,
    115			      <0x41600000 0x8000>,
    116			      <0x41700000 0x8000>;
    117			reg-names = "l2ram", "l1pram", "l1dram";
    118			ti,bootreg = <&scm_conf 0x560 10>;
    119			iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
    120			status = "disabled";
    121			resets = <&prm_dsp2 0>;
    122			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
    123			firmware-name = "dra7-dsp2-fw.xe66";
    124		};
    125	};
    126};
    127
    128&cpu0_opp_table {
    129	opp-shared;
    130};
    131
    132&dss {
    133	reg = <0 0x80>,
    134	      <0x4054 0x4>,
    135	      <0x4300 0x20>,
    136	      <0x9054 0x4>,
    137	      <0x9300 0x20>;
    138	reg-names = "dss", "pll1_clkctrl", "pll1",
    139		    "pll2_clkctrl", "pll2";
    140
    141	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
    142		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
    143		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
    144	clock-names = "fck", "video1_clk", "video2_clk";
    145};
    146
    147&mailbox5 {
    148	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
    149		ti,mbox-tx = <6 2 2>;
    150		ti,mbox-rx = <4 2 2>;
    151		status = "disabled";
    152	};
    153	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
    154		ti,mbox-tx = <5 2 2>;
    155		ti,mbox-rx = <1 2 2>;
    156		status = "disabled";
    157	};
    158};
    159
    160&mailbox6 {
    161	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
    162		ti,mbox-tx = <6 2 2>;
    163		ti,mbox-rx = <4 2 2>;
    164		status = "disabled";
    165	};
    166	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
    167		ti,mbox-tx = <5 2 2>;
    168		ti,mbox-rx = <1 2 2>;
    169		status = "disabled";
    170	};
    171};
    172
    173&pcie1_rc {
    174	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    175};
    176
    177&pcie1_ep {
    178	compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
    179};
    180
    181&pcie2_rc {
    182	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    183};
    184
    185&l4_per3 {
    186	segment@0 {
    187		usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
    188			compatible = "ti,sysc-omap4", "ti,sysc";
    189			reg = <0x140000 0x4>,
    190			      <0x140010 0x4>;
    191			reg-names = "rev", "sysc";
    192			ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
    193			ti,sysc-midle = <SYSC_IDLE_FORCE>,
    194					<SYSC_IDLE_NO>,
    195					<SYSC_IDLE_SMART>,
    196					<SYSC_IDLE_SMART_WKUP>;
    197			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
    198					<SYSC_IDLE_NO>,
    199					<SYSC_IDLE_SMART>,
    200					<SYSC_IDLE_SMART_WKUP>;
    201			/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
    202			clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
    203			clock-names = "fck";
    204			#address-cells = <1>;
    205			#size-cells = <1>;
    206			ranges = <0x0 0x140000 0x20000>;
    207
    208			omap_dwc3_4: omap_dwc3_4@0 {
    209				compatible = "ti,dwc3";
    210				reg = <0 0x10000>;
    211				interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
    212				#address-cells = <1>;
    213				#size-cells = <1>;
    214				utmi-mode = <2>;
    215				ranges;
    216				status = "disabled";
    217				usb4: usb@10000 {
    218					compatible = "snps,dwc3";
    219					reg = <0x10000 0x17000>;
    220					interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
    221						     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
    222						     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
    223					interrupt-names = "peripheral",
    224							  "host",
    225							  "otg";
    226					maximum-speed = "high-speed";
    227					dr_mode = "otg";
    228				};
    229			};
    230		};
    231	};
    232};