cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dra76-evm.dts (12118B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
      4 */
      5/dts-v1/;
      6
      7#include "dra76x.dtsi"
      8#include "dra7-evm-common.dtsi"
      9#include "dra76x-mmc-iodelay.dtsi"
     10#include <dt-bindings/net/ti-dp83867.h>
     11
     12/ {
     13	model = "TI DRA762 EVM";
     14	compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
     15
     16	aliases {
     17		display0 = &hdmi0;
     18
     19		sound0 = &sound0;
     20		sound1 = &hdmi;
     21	};
     22
     23	memory@0 {
     24		device_type = "memory";
     25		reg = <0x0 0x80000000 0x0 0x80000000>;
     26	};
     27
     28	reserved-memory {
     29		#address-cells = <2>;
     30		#size-cells = <2>;
     31		ranges;
     32
     33		ipu2_cma_pool: ipu2_cma@95800000 {
     34			compatible = "shared-dma-pool";
     35			reg = <0x0 0x95800000 0x0 0x3800000>;
     36			reusable;
     37			status = "okay";
     38		};
     39
     40		dsp1_cma_pool: dsp1_cma@99000000 {
     41			compatible = "shared-dma-pool";
     42			reg = <0x0 0x99000000 0x0 0x4000000>;
     43			reusable;
     44			status = "okay";
     45		};
     46
     47		ipu1_cma_pool: ipu1_cma@9d000000 {
     48			compatible = "shared-dma-pool";
     49			reg = <0x0 0x9d000000 0x0 0x2000000>;
     50			reusable;
     51			status = "okay";
     52		};
     53
     54		dsp2_cma_pool: dsp2_cma@9f000000 {
     55			compatible = "shared-dma-pool";
     56			reg = <0x0 0x9f000000 0x0 0x800000>;
     57			reusable;
     58			status = "okay";
     59		};
     60	};
     61
     62	vsys_12v0: fixedregulator-vsys12v0 {
     63		/* main supply */
     64		compatible = "regulator-fixed";
     65		regulator-name = "vsys_12v0";
     66		regulator-min-microvolt = <12000000>;
     67		regulator-max-microvolt = <12000000>;
     68		regulator-always-on;
     69		regulator-boot-on;
     70	};
     71
     72	vsys_5v0: fixedregulator-vsys5v0 {
     73		/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
     74		compatible = "regulator-fixed";
     75		regulator-name = "vsys_5v0";
     76		regulator-min-microvolt = <5000000>;
     77		regulator-max-microvolt = <5000000>;
     78		vin-supply = <&vsys_12v0>;
     79		regulator-always-on;
     80		regulator-boot-on;
     81	};
     82
     83	vio_3v6: fixedregulator-vio_3v6 {
     84		compatible = "regulator-fixed";
     85		regulator-name = "vio_3v6";
     86		regulator-min-microvolt = <3600000>;
     87		regulator-max-microvolt = <3600000>;
     88		vin-supply = <&vsys_5v0>;
     89		regulator-always-on;
     90		regulator-boot-on;
     91	};
     92
     93	vsys_3v3: fixedregulator-vsys3v3 {
     94		/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
     95		compatible = "regulator-fixed";
     96		regulator-name = "vsys_3v3";
     97		regulator-min-microvolt = <3300000>;
     98		regulator-max-microvolt = <3300000>;
     99		vin-supply = <&vsys_12v0>;
    100		regulator-always-on;
    101		regulator-boot-on;
    102	};
    103
    104	vio_3v3: fixedregulator-vio_3v3 {
    105		compatible = "regulator-fixed";
    106		regulator-name = "vio_3v3";
    107		regulator-min-microvolt = <3300000>;
    108		regulator-max-microvolt = <3300000>;
    109		vin-supply = <&vsys_3v3>;
    110		regulator-always-on;
    111		regulator-boot-on;
    112	};
    113
    114	vio_3v3_sd: fixedregulator-sd {
    115		compatible = "regulator-fixed";
    116		regulator-name = "vio_3v3_sd";
    117		regulator-min-microvolt = <3300000>;
    118		regulator-max-microvolt = <3300000>;
    119		vin-supply = <&vio_3v3>;
    120		enable-active-high;
    121		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
    122	};
    123
    124	vio_1v8: fixedregulator-vio_1v8 {
    125		compatible = "regulator-fixed";
    126		regulator-name = "vio_1v8";
    127		regulator-min-microvolt = <1800000>;
    128		regulator-max-microvolt = <1800000>;
    129		vin-supply = <&smps5_reg>;
    130	};
    131
    132	vmmcwl_fixed: fixedregulator-mmcwl {
    133		compatible = "regulator-fixed";
    134		regulator-name = "vmmcwl_fixed";
    135		regulator-min-microvolt = <1800000>;
    136		regulator-max-microvolt = <1800000>;
    137		gpio = <&gpio5 8 0>;	/* gpio5_8 */
    138		startup-delay-us = <70000>;
    139		enable-active-high;
    140	};
    141
    142	vtt_fixed: fixedregulator-vtt {
    143		compatible = "regulator-fixed";
    144		regulator-name = "vtt_fixed";
    145		regulator-min-microvolt = <1350000>;
    146		regulator-max-microvolt = <1350000>;
    147		vin-supply = <&vsys_3v3>;
    148		regulator-always-on;
    149		regulator-boot-on;
    150	};
    151
    152	aic_dvdd: fixedregulator-aic_dvdd {
    153		/* TPS77018DBVT */
    154		compatible = "regulator-fixed";
    155		regulator-name = "aic_dvdd";
    156		vin-supply = <&vio_3v3>;
    157		regulator-min-microvolt = <1800000>;
    158		regulator-max-microvolt = <1800000>;
    159	};
    160
    161	hdmi0: connector {
    162		compatible = "hdmi-connector";
    163		label = "hdmi";
    164
    165		type = "a";
    166
    167		port {
    168			hdmi_connector_in: endpoint {
    169				remote-endpoint = <&tpd12s015_out>;
    170			};
    171		};
    172	};
    173
    174	tpd12s015: encoder {
    175		compatible = "ti,tpd12s015";
    176
    177		gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>,   /* gpio7_30, CT CP HPD */
    178			<&gpio7 31 GPIO_ACTIVE_HIGH>,   /* gpio7_31, LS OE */
    179			<&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
    180
    181		ports {
    182			#address-cells = <1>;
    183			#size-cells = <0>;
    184
    185			port@0 {
    186				reg = <0>;
    187
    188				tpd12s015_in: endpoint {
    189					remote-endpoint = <&hdmi_out>;
    190				};
    191			};
    192
    193			port@1 {
    194				reg = <1>;
    195
    196				tpd12s015_out: endpoint {
    197					remote-endpoint = <&hdmi_connector_in>;
    198				};
    199			};
    200		};
    201	};
    202};
    203
    204&i2c1 {
    205	status = "okay";
    206	clock-frequency = <400000>;
    207
    208	tps65917: tps65917@58 {
    209		compatible = "ti,tps65917";
    210		reg = <0x58>;
    211		ti,system-power-controller;
    212		ti,palmas-override-powerhold;
    213		interrupt-controller;
    214		#interrupt-cells = <2>;
    215
    216		tps65917_pmic {
    217			compatible = "ti,tps65917-pmic";
    218
    219			smps12-in-supply = <&vsys_3v3>;
    220			smps3-in-supply = <&vsys_3v3>;
    221			smps4-in-supply = <&vsys_3v3>;
    222			smps5-in-supply = <&vsys_3v3>;
    223			ldo1-in-supply = <&vsys_3v3>;
    224			ldo2-in-supply = <&vsys_3v3>;
    225			ldo3-in-supply = <&vsys_5v0>;
    226			ldo4-in-supply = <&vsys_5v0>;
    227			ldo5-in-supply = <&vsys_3v3>;
    228
    229			tps65917_regulators: regulators {
    230				smps12_reg: smps12 {
    231					/* VDD_DSPEVE */
    232					regulator-name = "smps12";
    233					regulator-min-microvolt = <850000>;
    234					regulator-max-microvolt = <1250000>;
    235					regulator-always-on;
    236					regulator-boot-on;
    237				};
    238
    239				smps3_reg: smps3 {
    240					/* VDD_CORE */
    241					regulator-name = "smps3";
    242					regulator-min-microvolt = <850000>;
    243					regulator-max-microvolt = <1250000>;
    244					regulator-boot-on;
    245					regulator-always-on;
    246				};
    247
    248				smps4_reg: smps4 {
    249					/* VDD_IVA */
    250					regulator-name = "smps4";
    251					regulator-min-microvolt = <850000>;
    252					regulator-max-microvolt = <1250000>;
    253					regulator-always-on;
    254					regulator-boot-on;
    255				};
    256
    257				smps5_reg: smps5 {
    258					/* VDDS1V8 */
    259					regulator-name = "smps5";
    260					regulator-min-microvolt = <1800000>;
    261					regulator-max-microvolt = <1800000>;
    262					regulator-boot-on;
    263					regulator-always-on;
    264				};
    265
    266				ldo1_reg: ldo1 {
    267					/* LDO1_OUT --> VDA_PHY1_1V8  */
    268					regulator-name = "ldo1";
    269					regulator-min-microvolt = <1800000>;
    270					regulator-max-microvolt = <1800000>;
    271					regulator-always-on;
    272					regulator-boot-on;
    273					regulator-allow-bypass;
    274				};
    275
    276				ldo2_reg: ldo2 {
    277					/* LDO2_OUT --> VDA_PHY2_1V8 */
    278					regulator-name = "ldo2";
    279					regulator-min-microvolt = <1800000>;
    280					regulator-max-microvolt = <1800000>;
    281					regulator-allow-bypass;
    282					regulator-always-on;
    283				};
    284
    285				ldo3_reg: ldo3 {
    286					/* VDA_USB_3V3 */
    287					regulator-name = "ldo3";
    288					regulator-min-microvolt = <3300000>;
    289					regulator-max-microvolt = <3300000>;
    290					regulator-boot-on;
    291					regulator-always-on;
    292				};
    293
    294				ldo5_reg: ldo5 {
    295					/* VDDA_1V8_PLL */
    296					regulator-name = "ldo5";
    297					regulator-min-microvolt = <1800000>;
    298					regulator-max-microvolt = <1800000>;
    299					regulator-always-on;
    300					regulator-boot-on;
    301				};
    302
    303				ldo4_reg: ldo4 {
    304					/* VDD_SDIO_DV */
    305					regulator-name = "ldo4";
    306					regulator-min-microvolt = <1800000>;
    307					regulator-max-microvolt = <3300000>;
    308					regulator-boot-on;
    309					regulator-always-on;
    310				};
    311			};
    312		};
    313
    314		tps65917_power_button {
    315			compatible = "ti,palmas-pwrbutton";
    316			interrupt-parent = <&tps65917>;
    317			interrupts = <1 IRQ_TYPE_NONE>;
    318			wakeup-source;
    319			ti,palmas-long-press-seconds = <6>;
    320		};
    321	};
    322
    323	lp87565: lp87565@60 {
    324		compatible = "ti,lp87565-q1";
    325		reg = <0x60>;
    326
    327		buck10-in-supply =<&vsys_3v3>;
    328		buck23-in-supply =<&vsys_3v3>;
    329
    330		regulators: regulators {
    331			buck10_reg: buck10 {
    332				/*VDD_MPU*/
    333				regulator-name = "buck10";
    334				regulator-min-microvolt = <850000>;
    335				regulator-max-microvolt = <1250000>;
    336				regulator-always-on;
    337				regulator-boot-on;
    338			};
    339
    340			buck23_reg: buck23 {
    341				/* VDD_GPU*/
    342				regulator-name = "buck23";
    343				regulator-min-microvolt = <850000>;
    344				regulator-max-microvolt = <1250000>;
    345				regulator-boot-on;
    346				regulator-always-on;
    347			};
    348		};
    349	};
    350
    351	pcf_lcd: pcf8757@20 {
    352		compatible = "nxp,pcf8575";
    353		reg = <0x20>;
    354		gpio-controller;
    355		#gpio-cells = <2>;
    356		interrupt-controller;
    357		#interrupt-cells = <2>;
    358		interrupt-parent = <&gpio1>;
    359		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
    360	};
    361
    362	pcf_gpio_21: pcf8757@21 {
    363		compatible = "nxp,pcf8575";
    364		reg = <0x21>;
    365		gpio-controller;
    366		#gpio-cells = <2>;
    367		interrupt-parent = <&gpio1>;
    368		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
    369		interrupt-controller;
    370		#interrupt-cells = <2>;
    371	};
    372
    373	pcf_hdmi: pcf8575@26 {
    374		compatible = "nxp,pcf8575";
    375		reg = <0x26>;
    376		gpio-controller;
    377		#gpio-cells = <2>;
    378		hdmi-audio-hog {
    379			/* vin6_sel_s0: high: VIN6, low: audio */
    380			gpio-hog;
    381			gpios = <1 GPIO_ACTIVE_HIGH>;
    382			output-low;
    383			line-name = "vin6_sel_s0";
    384		};
    385	};
    386
    387	tlv320aic3106: tlv320aic3106@19 {
    388		#sound-dai-cells = <0>;
    389		compatible = "ti,tlv320aic3106";
    390		reg = <0x19>;
    391		adc-settle-ms = <40>;
    392		ai3x-micbias-vg = <1>;		/* 2.0V */
    393		status = "okay";
    394
    395		/* Regulators */
    396		AVDD-supply = <&vio_3v3>;
    397		IOVDD-supply = <&vio_3v3>;
    398		DRVDD-supply = <&vio_3v3>;
    399		DVDD-supply = <&aic_dvdd>;
    400	};
    401};
    402
    403&cpu0 {
    404	vdd-supply = <&buck10_reg>;
    405};
    406
    407&mmc1 {
    408	status = "okay";
    409	vmmc-supply = <&vio_3v3_sd>;
    410	vqmmc-supply = <&ldo4_reg>;
    411	bus-width = <4>;
    412	/*
    413	 * SDCD signal is not being used here - using the fact that GPIO mode
    414	 * is always hardwired.
    415	 */
    416	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
    417	pinctrl-names = "default", "hs";
    418	pinctrl-0 = <&mmc1_pins_default>;
    419	pinctrl-1 = <&mmc1_pins_hs>;
    420};
    421
    422&mmc2 {
    423	status = "okay";
    424	vmmc-supply = <&vio_1v8>;
    425	vqmmc-supply = <&vio_1v8>;
    426	bus-width = <8>;
    427	non-removable;
    428	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
    429	pinctrl-0 = <&mmc2_pins_default>;
    430	pinctrl-1 = <&mmc2_pins_default>;
    431	pinctrl-2 = <&mmc2_pins_default>;
    432	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
    433};
    434
    435&mmc4 {
    436	status = "okay";
    437	vmmc-supply = <&vio_3v6>;
    438	vqmmc-supply = <&vmmcwl_fixed>;
    439	pinctrl-names = "default", "hs", "sdr12", "sdr25";
    440	pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>;
    441	pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
    442	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
    443	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
    444};
    445
    446/* No RTC on this device */
    447&rtc {
    448	status = "disabled";
    449};
    450
    451&mac_sw {
    452	status = "okay";
    453};
    454
    455&cpsw_port1 {
    456	phy-handle = <&dp83867_0>;
    457	phy-mode = "rgmii-id";
    458	ti,dual-emac-pvid = <1>;
    459};
    460
    461&cpsw_port2 {
    462	phy-handle = <&dp83867_1>;
    463	phy-mode = "rgmii-id";
    464	ti,dual-emac-pvid = <2>;
    465};
    466
    467&davinci_mdio_sw {
    468	dp83867_0: ethernet-phy@2 {
    469		reg = <2>;
    470		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
    471		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
    472		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
    473		ti,min-output-impedance;
    474		ti,dp83867-rxctrl-strap-quirk;
    475	};
    476
    477	dp83867_1: ethernet-phy@3 {
    478		reg = <3>;
    479		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
    480		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
    481		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
    482		ti,min-output-impedance;
    483		ti,dp83867-rxctrl-strap-quirk;
    484	};
    485};
    486
    487&usb2_phy1 {
    488	phy-supply = <&ldo3_reg>;
    489};
    490
    491&usb2_phy2 {
    492	phy-supply = <&ldo3_reg>;
    493};
    494
    495&dss {
    496	status = "okay";
    497	vdda_video-supply = <&ldo5_reg>;
    498};
    499
    500&hdmi {
    501	status = "okay";
    502
    503	vdda-supply = <&ldo1_reg>;
    504
    505	port {
    506		hdmi_out: endpoint {
    507			remote-endpoint = <&tpd12s015_in>;
    508		};
    509	};
    510};
    511
    512&qspi {
    513	spi-max-frequency = <96000000>;
    514	flash@0 {
    515		spi-max-frequency = <96000000>;
    516	};
    517};
    518
    519&pcie2_phy {
    520	status = "okay";
    521};
    522
    523&pcie1_rc {
    524	num-lanes = <2>;
    525	phys = <&pcie1_phy>, <&pcie2_phy>;
    526	phy-names = "pcie-phy0", "pcie-phy1";
    527};
    528
    529&pcie1_ep {
    530	num-lanes = <2>;
    531	phys = <&pcie1_phy>, <&pcie2_phy>;
    532	phy-names = "pcie-phy0", "pcie-phy1";
    533};
    534
    535&extcon_usb1 {
    536	vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
    537};
    538
    539&extcon_usb2 {
    540	vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
    541};
    542
    543&m_can0 {
    544	can-transceiver {
    545		max-bitrate = <5000000>;
    546	};
    547};
    548
    549&ipu2 {
    550	status = "okay";
    551	memory-region = <&ipu2_cma_pool>;
    552};
    553
    554&ipu1 {
    555	status = "okay";
    556	memory-region = <&ipu1_cma_pool>;
    557};
    558
    559&dsp1 {
    560	status = "okay";
    561	memory-region = <&dsp1_cma_pool>;
    562};
    563
    564&dsp2 {
    565	status = "okay";
    566	memory-region = <&dsp2_cma_pool>;
    567};