cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

exynos5422-odroidxu4.dts (1919B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Hardkernel Odroid XU4 board device tree source
      4 *
      5 * Copyright (c) 2015 Krzysztof Kozlowski
      6 * Copyright (c) 2014 Collabora Ltd.
      7 * Copyright (c) 2013-2015 Samsung Electronics Co., Ltd.
      8 *		http://www.samsung.com
      9 */
     10
     11/dts-v1/;
     12#include <dt-bindings/sound/samsung-i2s.h>
     13#include "exynos5422-odroidxu3-common.dtsi"
     14
     15/ {
     16	model = "Hardkernel Odroid XU4";
     17	compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \
     18		     "samsung,exynos5";
     19
     20	led-controller {
     21		compatible = "pwm-leds";
     22
     23		led-1 {
     24			label = "blue:heartbeat";
     25			pwms = <&pwm 2 2000000 0>;
     26			pwm-names = "pwm2";
     27			max-brightness = <255>;
     28			linux,default-trigger = "heartbeat";
     29		};
     30	};
     31
     32	sound: sound {
     33		compatible = "samsung,odroid-xu3-audio";
     34		model = "Odroid-XU4";
     35
     36		samsung,audio-routing = "I2S Playback", "Mixer DAI TX";
     37
     38		cpu {
     39			sound-dai = <&i2s0 0>, <&i2s0 1>;
     40		};
     41
     42		codec {
     43			sound-dai = <&hdmi>;
     44		};
     45	};
     46};
     47
     48&i2s0 {
     49	status = "okay";
     50
     51	assigned-clocks = <&clock CLK_MOUT_EPLL>,
     52			  <&clock CLK_MOUT_MAU_EPLL>,
     53			  <&clock CLK_MOUT_USER_MAU_EPLL>,
     54			  <&clock_audss EXYNOS_MOUT_AUDSS>,
     55			  <&clock_audss EXYNOS_MOUT_I2S>,
     56			  <&i2s0 CLK_I2S_RCLK_SRC>,
     57			  <&clock_audss EXYNOS_DOUT_SRP>,
     58			  <&clock_audss EXYNOS_DOUT_AUD_BUS>,
     59			  <&clock_audss EXYNOS_DOUT_I2S>;
     60
     61	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
     62				 <&clock CLK_MOUT_EPLL>,
     63				 <&clock CLK_MOUT_MAU_EPLL>,
     64				 <&clock CLK_MAU_EPLL>,
     65				 <&clock_audss EXYNOS_MOUT_AUDSS>,
     66				 <&clock_audss EXYNOS_SCLK_I2S>;
     67
     68	assigned-clock-rates = <0>,
     69			       <0>,
     70			       <0>,
     71			       <0>,
     72			       <0>,
     73			       <0>,
     74			       <196608001>,
     75			       <(196608002 / 2)>,
     76			       <196608000>;
     77};
     78
     79&pwm {
     80	/*
     81	 * PWM 0 -- fan
     82	 * PWM 2 -- Blue LED
     83	 */
     84	pinctrl-0 = <&pwm0_out &pwm2_out>;
     85	pinctrl-names = "default";
     86	samsung,pwm-outputs = <0>, <2>;
     87	status = "okay";
     88};
     89
     90&usbdrd_dwc3_1 {
     91	dr_mode = "host";
     92};