cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

imx1-ads.dts (2502B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
      4 */
      5
      6/dts-v1/;
      7#include "imx1.dtsi"
      8
      9/ {
     10	model = "Freescale MX1 ADS";
     11	compatible = "fsl,imx1ads", "fsl,imx1";
     12
     13	chosen {
     14		stdout-path = &uart1;
     15	};
     16
     17	memory@8000000 {
     18		device_type = "memory";
     19		reg = <0x08000000 0x04000000>;
     20	};
     21};
     22
     23&cspi1 {
     24	pinctrl-0 = <&pinctrl_cspi1>;
     25	cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
     26	status = "okay";
     27};
     28
     29&i2c {
     30	pinctrl-names = "default";
     31	pinctrl-0 = <&pinctrl_i2c>;
     32	status = "okay";
     33
     34	extgpio0: pcf8575@22 {
     35		compatible = "nxp,pcf8575";
     36		reg = <0x22>;
     37		gpio-controller;
     38		#gpio-cells = <2>;
     39	};
     40
     41	extgpio1: pcf8575@24 {
     42		compatible = "nxp,pcf8575";
     43		reg = <0x24>;
     44		gpio-controller;
     45		#gpio-cells = <2>;
     46	};
     47};
     48
     49&uart1 {
     50	pinctrl-names = "default";
     51	pinctrl-0 = <&pinctrl_uart1>;
     52	uart-has-rtscts;
     53	status = "okay";
     54};
     55
     56&uart2 {
     57	pinctrl-names = "default";
     58	pinctrl-0 = <&pinctrl_uart2>;
     59	uart-has-rtscts;
     60	status = "okay";
     61};
     62
     63&weim {
     64	pinctrl-names = "default";
     65	pinctrl-0 = <&pinctrl_weim>;
     66	status = "okay";
     67
     68	nor: nor@0,0 {
     69		compatible = "cfi-flash";
     70		reg = <0 0x00000000 0x02000000>;
     71		bank-width = <4>;
     72		fsl,weim-cs-timing = <0x00003e00 0x00000801>;
     73		#address-cells = <1>;
     74		#size-cells = <1>;
     75	};
     76};
     77
     78&iomuxc {
     79	imx1-ads {
     80		pinctrl_cspi1: cspi1grp {
     81			fsl,pins = <
     82				MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
     83				MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
     84				MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
     85				MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
     86				MX1_PAD_SPI1_SS__GPIO3_15	0x0
     87			>;
     88		};
     89
     90		pinctrl_i2c: i2cgrp {
     91			fsl,pins = <
     92				MX1_PAD_I2C_SCL__I2C_SCL	0x0
     93				MX1_PAD_I2C_SDA__I2C_SDA	0x0
     94			>;
     95		};
     96
     97		pinctrl_uart1: uart1grp {
     98			fsl,pins = <
     99				MX1_PAD_UART1_TXD__UART1_TXD	0x0
    100				MX1_PAD_UART1_RXD__UART1_RXD	0x0
    101				MX1_PAD_UART1_CTS__UART1_CTS	0x0
    102				MX1_PAD_UART1_RTS__UART1_RTS	0x0
    103			>;
    104		};
    105
    106		pinctrl_uart2: uart2grp {
    107			fsl,pins = <
    108				MX1_PAD_UART2_TXD__UART2_TXD	0x0
    109				MX1_PAD_UART2_RXD__UART2_RXD	0x0
    110				MX1_PAD_UART2_CTS__UART2_CTS	0x0
    111				MX1_PAD_UART2_RTS__UART2_RTS	0x0
    112			>;
    113		};
    114
    115		pinctrl_weim: weimgrp {
    116			fsl,pins = <
    117				MX1_PAD_A0__A0			0x0
    118				MX1_PAD_A16__A16		0x0
    119				MX1_PAD_A17__A17		0x0
    120				MX1_PAD_A18__A18		0x0
    121				MX1_PAD_A19__A19		0x0
    122				MX1_PAD_A20__A20		0x0
    123				MX1_PAD_A21__A21		0x0
    124				MX1_PAD_A22__A22		0x0
    125				MX1_PAD_A23__A23		0x0
    126				MX1_PAD_A24__A24		0x0
    127				MX1_PAD_BCLK__BCLK		0x0
    128				MX1_PAD_CS4__CS4		0x0
    129				MX1_PAD_DTACK__DTACK		0x0
    130				MX1_PAD_ECB__ECB		0x0
    131				MX1_PAD_LBA__LBA		0x0
    132			>;
    133		};
    134	};
    135};