cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx25-eukrea-mbimxsd25-baseboard.dts (3693B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
      4 */
      5
      6/dts-v1/;
      7
      8#include <dt-bindings/gpio/gpio.h>
      9#include <dt-bindings/input/input.h>
     10#include "imx25-eukrea-cpuimx25.dtsi"
     11
     12/ {
     13	model = "Eukrea MBIMXSD25";
     14	compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
     15
     16	gpio_keys {
     17		compatible = "gpio-keys";
     18		pinctrl-names = "default";
     19		pinctrl-0 = <&pinctrl_gpiokeys>;
     20
     21		bp1 {
     22			label = "BP1";
     23			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
     24			linux,code = <BTN_MISC>;
     25			wakeup-source;
     26		};
     27	};
     28
     29	leds {
     30		compatible = "gpio-leds";
     31		pinctrl-names = "default";
     32		pinctrl-0 = <&pinctrl_gpioled>;
     33
     34		led1 {
     35			label = "led1";
     36			gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
     37			linux,default-trigger = "heartbeat";
     38		};
     39	};
     40
     41	sound {
     42		compatible = "eukrea,asoc-tlv320";
     43		eukrea,model = "imx25-eukrea-tlv320aic23";
     44		ssi-controller = <&ssi1>;
     45		fsl,mux-int-port = <1>;
     46		fsl,mux-ext-port = <5>;
     47	};
     48};
     49
     50&audmux {
     51	pinctrl-names = "default";
     52	pinctrl-0 = <&pinctrl_audmux>;
     53	status = "okay";
     54};
     55
     56&esdhc1 {
     57	pinctrl-names = "default";
     58	pinctrl-0 = <&pinctrl_esdhc1>;
     59	cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
     60	status = "okay";
     61};
     62
     63&i2c1 {
     64	tlv320aic23: codec@1a {
     65		compatible = "ti,tlv320aic23";
     66		reg = <0x1a>;
     67	};
     68};
     69
     70&iomuxc {
     71	imx25-eukrea-mbimxsd25-baseboard {
     72		pinctrl_audmux: audmuxgrp {
     73			fsl,pins = <
     74				MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
     75				MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
     76				MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
     77				MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
     78			>;
     79		};
     80
     81		pinctrl_esdhc1: esdhc1grp {
     82			fsl,pins = <
     83				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
     84				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
     85				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
     86				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
     87				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
     88				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
     89			>;
     90		};
     91
     92		pinctrl_gpiokeys: gpiokeysgrp {
     93			fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
     94		};
     95
     96		pinctrl_gpioled: gpioledgrp {
     97			fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
     98		};
     99
    100		pinctrl_lcdc: lcdcgrp {
    101			fsl,pins = <
    102				MX25_PAD_LD0__LD0			0x1
    103				MX25_PAD_LD1__LD1			0x1
    104				MX25_PAD_LD2__LD2			0x1
    105				MX25_PAD_LD3__LD3			0x1
    106				MX25_PAD_LD4__LD4			0x1
    107				MX25_PAD_LD5__LD5			0x1
    108				MX25_PAD_LD6__LD6			0x1
    109				MX25_PAD_LD7__LD7			0x1
    110				MX25_PAD_LD8__LD8			0x1
    111				MX25_PAD_LD9__LD9			0x1
    112				MX25_PAD_LD10__LD10			0x1
    113				MX25_PAD_LD11__LD11			0x1
    114				MX25_PAD_LD12__LD12			0x1
    115				MX25_PAD_LD13__LD13			0x1
    116				MX25_PAD_LD14__LD14			0x1
    117				MX25_PAD_LD15__LD15			0x1
    118				MX25_PAD_GPIO_E__LD16			0x1
    119				MX25_PAD_GPIO_F__LD17			0x1
    120				MX25_PAD_HSYNC__HSYNC			0x80000000
    121				MX25_PAD_VSYNC__VSYNC			0x80000000
    122				MX25_PAD_LSCLK__LSCLK			0x80000000
    123				MX25_PAD_OE_ACD__OE_ACD			0x80000000
    124				MX25_PAD_CONTRAST__CONTRAST		0x80000000
    125			>;
    126		};
    127
    128		pinctrl_uart1: uart1grp {
    129			fsl,pins = <
    130				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
    131				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
    132				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
    133				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
    134			>;
    135		};
    136
    137		pinctrl_uart2: uart2grp {
    138			fsl,pins = <
    139				MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
    140				MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
    141				MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
    142				MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
    143			>;
    144		};
    145	};
    146};
    147
    148&ssi1 {
    149	codec-handle = <&tlv320aic23>;
    150	status = "okay";
    151};
    152
    153&uart1 {
    154	pinctrl-names = "default";
    155	pinctrl-0 = <&pinctrl_uart1>;
    156	uart-has-rtscts;
    157	status = "okay";
    158};
    159
    160&uart2 {
    161	pinctrl-names = "default";
    162	pinctrl-0 = <&pinctrl_uart2>;
    163	uart-has-rtscts;
    164	status = "okay";
    165};
    166
    167&usbhost1 {
    168	status = "okay";
    169};
    170
    171&usbotg {
    172	external-vbus-divider;
    173	status = "okay";
    174};