cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

imx27-pdk.dts (4196B)

      1// SPDX-License-Identifier: GPL-2.0+
      2//
      3// Copyright 2012 Sascha Hauer, Pengutronix
      4
      5/dts-v1/;
      6#include "imx27.dtsi"
      7
      8/ {
      9	model = "Freescale i.MX27 Product Development Kit";
     10	compatible = "fsl,imx27-pdk", "fsl,imx27";
     11
     12	memory@a0000000 {
     13		device_type = "memory";
     14		reg = <0xa0000000 0x08000000>;
     15	};
     16
     17	usbphy {
     18		compatible = "simple-bus";
     19		#address-cells = <1>;
     20		#size-cells = <0>;
     21
     22		usbphy0: usbphy@0 {
     23			compatible = "usb-nop-xceiv";
     24			reg = <0>;
     25			clocks = <&clks IMX27_CLK_DUMMY>;
     26			clock-names = "main_clk";
     27			#phy-cells = <0>;
     28		};
     29	};
     30};
     31
     32&cspi2 {
     33	pinctrl-names = "default";
     34	pinctrl-0 = <&pinctrl_cspi2>;
     35	cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
     36	status = "okay";
     37
     38	pmic: mc13783@0 {
     39		compatible = "fsl,mc13783";
     40		reg = <0>;
     41		spi-cs-high;
     42		spi-max-frequency = <1000000>;
     43		interrupt-parent = <&gpio3>;
     44		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
     45
     46		regulators {
     47			vgen_reg: vgen {
     48				regulator-min-microvolt = <1500000>;
     49				regulator-max-microvolt = <1500000>;
     50				regulator-always-on;
     51				regulator-boot-on;
     52			};
     53
     54			vmmc1_reg: vmmc1 {
     55				regulator-min-microvolt = <1600000>;
     56				regulator-max-microvolt = <3000000>;
     57			};
     58
     59			gpo1_reg: gpo1 {
     60				regulator-always-on;
     61				regulator-boot-on;
     62			};
     63
     64			gpo3_reg: gpo3 {
     65				regulator-always-on;
     66				regulator-boot-on;
     67			};
     68		};
     69	};
     70};
     71
     72&fec {
     73	phy-mode = "mii";
     74	pinctrl-names = "default";
     75	pinctrl-0 = <&pinctrl_fec>;
     76	status = "okay";
     77};
     78
     79&kpp {
     80	linux,keymap = <
     81		MATRIX_KEY(0, 0, KEY_UP)
     82		MATRIX_KEY(0, 1, KEY_DOWN)
     83		MATRIX_KEY(1, 0, KEY_RIGHT)
     84		MATRIX_KEY(1, 1, KEY_LEFT)
     85		MATRIX_KEY(1, 2, KEY_ENTER)
     86		MATRIX_KEY(2, 0, KEY_F6)
     87		MATRIX_KEY(2, 1, KEY_F8)
     88		MATRIX_KEY(2, 2, KEY_F9)
     89		MATRIX_KEY(2, 3, KEY_F10)
     90	>;
     91	status = "okay";
     92};
     93
     94&nfc {
     95	pinctrl-names = "default";
     96	pinctrl-0 = <&pinctrl_nand>;
     97	nand-ecc-mode = "hw";
     98	nand-on-flash-bbt;
     99	status = "okay";
    100};
    101
    102&uart1 {
    103	uart-has-rtscts;
    104	pinctrl-names = "default";
    105	pinctrl-0 = <&pinctrl_uart1>;
    106	status = "okay";
    107};
    108
    109&usbotg {
    110	pinctrl-names = "default";
    111	pinctrl-0 = <&pinctrl_usbotg>;
    112	dr_mode = "otg";
    113	fsl,usbphy = <&usbphy0>;
    114	phy_type = "ulpi";
    115	status = "okay";
    116};
    117
    118&iomuxc {
    119	imx27-pdk {
    120		pinctrl_cspi2: cspi2grp {
    121			fsl,pins = <
    122				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
    123				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
    124				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
    125				MX27_PAD_CSPI2_SS0__GPIO4_21	0x0 /* SPI2 CS0 */
    126				MX27_PAD_TOUT__GPIO3_14		0x0 /* PMIC IRQ */
    127			>;
    128		};
    129
    130		pinctrl_fec: fecgrp {
    131			fsl,pins = <
    132				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
    133				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
    134				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
    135				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
    136				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
    137				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
    138				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
    139				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
    140				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
    141				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
    142				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
    143				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
    144				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
    145				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
    146				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
    147				MX27_PAD_ATA_DATA13__FEC_COL 0x0
    148				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
    149				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
    150			>;
    151		};
    152
    153		pinctrl_nand: nandgrp {
    154			fsl,pins = <
    155				MX27_PAD_NFRB__NFRB	0x0
    156				MX27_PAD_NFCLE__NFCLE	0x0
    157				MX27_PAD_NFWP_B__NFWP_B	0x0
    158				MX27_PAD_NFCE_B__NFCE_B	0x0
    159				MX27_PAD_NFALE__NFALE	0x0
    160				MX27_PAD_NFRE_B__NFRE_B	0x0
    161				MX27_PAD_NFWE_B__NFWE_B	0x0
    162			>;
    163		};
    164
    165		pinctrl_uart1: uart1grp {
    166			fsl,pins = <
    167				MX27_PAD_UART1_TXD__UART1_TXD 0x0
    168				MX27_PAD_UART1_RXD__UART1_RXD 0x0
    169				MX27_PAD_UART1_CTS__UART1_CTS 0x0
    170				MX27_PAD_UART1_RTS__UART1_RTS 0x0
    171			>;
    172		};
    173
    174		pinctrl_usbotg: usbotggrp {
    175			fsl,pins = <
    176				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
    177				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
    178				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
    179				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
    180				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
    181				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
    182				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
    183				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
    184				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
    185				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
    186				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
    187				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
    188			>;
    189		};
    190	};
    191};