cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx27-phytec-phycard-s-som.dtsi (2043B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
      4 * and Markus Pargmann, Pengutronix
      5 */
      6
      7/dts-v1/;
      8#include "imx27.dtsi"
      9
     10/ {
     11	model = "Phytec pca100";
     12	compatible = "phytec,imx27-pca100", "fsl,imx27";
     13
     14	memory@a0000000 {
     15		device_type = "memory";
     16		reg = <0xa0000000 0x08000000>; /* 128MB */
     17	};
     18};
     19
     20&cspi1 {
     21	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
     22		   <&gpio4 27 GPIO_ACTIVE_LOW>;
     23	status = "okay";
     24};
     25
     26&fec {
     27	pinctrl-names = "default";
     28	pinctrl-0 = <&pinctrl_fec1>;
     29	status = "okay";
     30};
     31
     32&i2c2 {
     33	pinctrl-names = "default";
     34	pinctrl-0 = <&pinctrl_i2c2>;
     35	status = "okay";
     36
     37	at24@52 {
     38		compatible = "atmel,24c32";
     39		pagesize = <32>;
     40		reg = <0x52>;
     41	};
     42};
     43
     44&iomuxc {
     45	imx27-phycard-s-som {
     46		pinctrl_fec1: fec1grp {
     47			fsl,pins = <
     48				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
     49				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
     50				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
     51				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
     52				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
     53				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
     54				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
     55				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
     56				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
     57				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
     58				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
     59				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
     60				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
     61				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
     62				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
     63				MX27_PAD_ATA_DATA13__FEC_COL 0x0
     64				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
     65				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
     66			>;
     67		};
     68
     69		pinctrl_i2c2: i2c2grp {
     70			fsl,pins = <
     71				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
     72				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
     73			>;
     74		};
     75
     76		pinctrl_nfc: nfcgrp {
     77			fsl,pins = <
     78				MX27_PAD_NFRB__NFRB 0x0
     79				MX27_PAD_NFCLE__NFCLE 0x0
     80				MX27_PAD_NFWP_B__NFWP_B 0x0
     81				MX27_PAD_NFCE_B__NFCE_B 0x0
     82				MX27_PAD_NFALE__NFALE 0x0
     83				MX27_PAD_NFRE_B__NFRE_B 0x0
     84				MX27_PAD_NFWE_B__NFWE_B 0x0
     85			>;
     86		};
     87	};
     88};
     89
     90&nfc {
     91	pinctrl-names = "default";
     92	pinctrl-0 = <&pinctrl_nfc>;
     93	nand-bus-width = <8>;
     94	nand-ecc-mode = "hw";
     95	nand-on-flash-bbt;
     96	status = "okay";
     97};