cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx27-phytec-phycore-rdk.dts (6410B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 */
      4
      5#include "imx27-phytec-phycore-som.dtsi"
      6
      7/ {
      8	model = "Phytec pcm970";
      9	compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
     10
     11	chosen {
     12		stdout-path = &uart1;
     13	};
     14
     15	display0: LQ035Q7 {
     16		model = "Sharp-LQ035Q7";
     17		bits-per-pixel = <16>;
     18		fsl,pcr = <0xf00080c0>;
     19
     20		display-timings {
     21			native-mode = <&timing0>;
     22			timing0: 240x320 {
     23				clock-frequency = <5500000>;
     24				hactive = <240>;
     25				vactive = <320>;
     26				hback-porch = <5>;
     27				hsync-len = <7>;
     28				hfront-porch = <16>;
     29				vback-porch = <7>;
     30				vsync-len = <1>;
     31				vfront-porch = <9>;
     32				pixelclk-active = <1>;
     33				hsync-active = <1>;
     34				vsync-active = <1>;
     35				de-active = <0>;
     36			};
     37		};
     38	};
     39
     40	regulators {
     41		regulator@2 {
     42			compatible = "regulator-fixed";
     43			pinctrl-names = "default";
     44			pinctrl-0 = <&pinctrl_csien>;
     45			reg = <2>;
     46			regulator-name = "CSI_EN";
     47			regulator-min-microvolt = <3300000>;
     48			regulator-max-microvolt = <3300000>;
     49			gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
     50			regulator-always-on;
     51		};
     52	};
     53
     54	usbphy {
     55		usbphy2: usbphy@2 {
     56			compatible = "usb-nop-xceiv";
     57			reg = <2>;
     58			vcc-supply = <&reg_5v0>;
     59			clocks = <&clks IMX27_CLK_DUMMY>;
     60			clock-names = "main_clk";
     61			#phy-cells = <0>;
     62		};
     63	};
     64};
     65
     66&cspi1 {
     67	pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
     68	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
     69		   <&gpio4 27 GPIO_ACTIVE_LOW>;
     70};
     71
     72&fb {
     73	pinctrl-names = "default";
     74	pinctrl-0 = <&pinctrl_imxfb1>;
     75	display = <&display0>;
     76	lcd-supply = <&reg_5v0>;
     77	fsl,dmacr = <0x00020010>;
     78	fsl,lscr1 = <0x00120300>;
     79	fsl,lpccr = <0x00a903ff>;
     80	status = "okay";
     81};
     82
     83&i2c1 {
     84	clock-frequency = <400000>;
     85	pinctrl-names = "default";
     86	pinctrl-0 = <&pinctrl_i2c1>;
     87	status = "okay";
     88
     89	camgpio: pca9536@41 {
     90		compatible = "nxp,pca9536";
     91		reg = <0x41>;
     92		gpio-controller;
     93		#gpio-cells = <2>;
     94	};
     95};
     96
     97&iomuxc {
     98	imx27_phycore_rdk {
     99		pinctrl_csien: csiengrp {
    100			fsl,pins = <
    101				MX27_PAD_USB_OC_B__GPIO2_24 0x0
    102			>;
    103		};
    104
    105		pinctrl_cspi1cs1: cspi1cs1grp {
    106			fsl,pins = <
    107				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
    108			>;
    109		};
    110
    111		pinctrl_imxfb1: imxfbgrp {
    112			fsl,pins = <
    113				MX27_PAD_LD0__LD0 0x0
    114				MX27_PAD_LD1__LD1 0x0
    115				MX27_PAD_LD2__LD2 0x0
    116				MX27_PAD_LD3__LD3 0x0
    117				MX27_PAD_LD4__LD4 0x0
    118				MX27_PAD_LD5__LD5 0x0
    119				MX27_PAD_LD6__LD6 0x0
    120				MX27_PAD_LD7__LD7 0x0
    121				MX27_PAD_LD8__LD8 0x0
    122				MX27_PAD_LD9__LD9 0x0
    123				MX27_PAD_LD10__LD10 0x0
    124				MX27_PAD_LD11__LD11 0x0
    125				MX27_PAD_LD12__LD12 0x0
    126				MX27_PAD_LD13__LD13 0x0
    127				MX27_PAD_LD14__LD14 0x0
    128				MX27_PAD_LD15__LD15 0x0
    129				MX27_PAD_LD16__LD16 0x0
    130				MX27_PAD_LD17__LD17 0x0
    131				MX27_PAD_CLS__CLS 0x0
    132				MX27_PAD_CONTRAST__CONTRAST 0x0
    133				MX27_PAD_LSCLK__LSCLK 0x0
    134				MX27_PAD_OE_ACD__OE_ACD 0x0
    135				MX27_PAD_PS__PS 0x0
    136				MX27_PAD_REV__REV 0x0
    137				MX27_PAD_SPL_SPR__SPL_SPR 0x0
    138				MX27_PAD_HSYNC__HSYNC 0x0
    139				MX27_PAD_VSYNC__VSYNC 0x0
    140			>;
    141		};
    142
    143		pinctrl_i2c1: i2c1grp {
    144			/* Add pullup to DATA line */
    145			fsl,pins = <
    146				MX27_PAD_I2C_DATA__I2C_DATA	0x1
    147				MX27_PAD_I2C_CLK__I2C_CLK	0x0
    148			>;
    149		};
    150
    151		pinctrl_owire1: owire1grp {
    152			fsl,pins = <
    153				MX27_PAD_RTCK__OWIRE 0x0
    154			>;
    155		};
    156
    157		pinctrl_sdhc2: sdhc2grp {
    158			fsl,pins = <
    159				MX27_PAD_SD2_CLK__SD2_CLK 0x0
    160				MX27_PAD_SD2_CMD__SD2_CMD 0x0
    161				MX27_PAD_SD2_D0__SD2_D0 0x0
    162				MX27_PAD_SD2_D1__SD2_D1 0x0
    163				MX27_PAD_SD2_D2__SD2_D2 0x0
    164				MX27_PAD_SD2_D3__SD2_D3 0x0
    165				MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
    166				MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
    167			>;
    168		};
    169
    170		pinctrl_uart1: uart1grp {
    171			fsl,pins = <
    172				MX27_PAD_UART1_TXD__UART1_TXD 0x0
    173				MX27_PAD_UART1_RXD__UART1_RXD 0x0
    174				MX27_PAD_UART1_CTS__UART1_CTS 0x0
    175				MX27_PAD_UART1_RTS__UART1_RTS 0x0
    176			>;
    177		};
    178
    179		pinctrl_uart2: uart2grp {
    180			fsl,pins = <
    181				MX27_PAD_UART2_TXD__UART2_TXD 0x0
    182				MX27_PAD_UART2_RXD__UART2_RXD 0x0
    183				MX27_PAD_UART2_CTS__UART2_CTS 0x0
    184				MX27_PAD_UART2_RTS__UART2_RTS 0x0
    185			>;
    186		};
    187
    188		pinctrl_usbh2: usbh2grp {
    189			fsl,pins = <
    190				MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
    191				MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
    192				MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
    193				MX27_PAD_USBH2_STP__USBH2_STP 0x0
    194				MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
    195				MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
    196				MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
    197				MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
    198				MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
    199				MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
    200				MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
    201				MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
    202			>;
    203		};
    204
    205		pinctrl_weim: weimgrp {
    206			fsl,pins = <
    207				MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
    208				MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
    209			>;
    210		};
    211	};
    212};
    213
    214&owire {
    215	pinctrl-names = "default";
    216	pinctrl-0 = <&pinctrl_owire1>;
    217	status = "okay";
    218};
    219
    220&pmicleds {
    221	ledr1: led@3 {
    222		reg = <3>;
    223		label = "system:red1:user";
    224	};
    225
    226	ledg1: led@4 {
    227		reg = <4>;
    228		label = "system:green1:user";
    229	};
    230
    231	ledb1: led@5 {
    232		reg = <5>;
    233		label = "system:blue1:user";
    234	};
    235
    236	ledr2: led@6 {
    237		reg = <6>;
    238		label = "system:red2:user";
    239	};
    240
    241	ledg2: led@7 {
    242		reg = <7>;
    243		label = "system:green2:user";
    244	};
    245
    246	ledb2: led@8 {
    247		reg = <8>;
    248		label = "system:blue2:user";
    249	};
    250
    251	ledr3: led@9 {
    252		reg = <9>;
    253		label = "system:red3:nand";
    254		linux,default-trigger = "nand-disk";
    255	};
    256
    257	ledg3: led@10 {
    258		reg = <10>;
    259		label = "system:green3:live";
    260		linux,default-trigger = "heartbeat";
    261	};
    262
    263	ledb3: led@11 {
    264		reg = <11>;
    265		label = "system:blue3:cpu";
    266		linux,default-trigger = "cpu0";
    267	};
    268};
    269
    270&sdhci2 {
    271	pinctrl-names = "default";
    272	pinctrl-0 = <&pinctrl_sdhc2>;
    273	bus-width = <4>;
    274	cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
    275	wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
    276	vmmc-supply = <&vmmc1_reg>;
    277	status = "okay";
    278};
    279
    280&uart1 {
    281	uart-has-rtscts;
    282	pinctrl-names = "default";
    283	pinctrl-0 = <&pinctrl_uart1>;
    284	status = "okay";
    285};
    286
    287&uart2 {
    288	uart-has-rtscts;
    289	pinctrl-names = "default";
    290	pinctrl-0 = <&pinctrl_uart2>;
    291	status = "okay";
    292};
    293
    294&usbh2 {
    295	pinctrl-names = "default";
    296	pinctrl-0 = <&pinctrl_usbh2>;
    297	dr_mode = "host";
    298	phy_type = "ulpi";
    299	vbus-supply = <&reg_5v0>;
    300	fsl,usbphy = <&usbphy2>;
    301	disable-over-current;
    302	status = "okay";
    303};
    304
    305&weim {
    306	pinctrl-names = "default";
    307	pinctrl-0 = <&pinctrl_weim>;
    308
    309	can@4,0 {
    310		compatible = "nxp,sja1000";
    311		reg = <4 0x00000000 0x00000100>;
    312		interrupt-parent = <&gpio5>;
    313		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
    314		nxp,external-clock-frequency = <16000000>;
    315		nxp,tx-output-config = <0x16>;
    316		nxp,no-comparator-bypass;
    317		fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
    318	};
    319};