cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx28-cfa10056.dts (2680B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 2013 Free Electrons
      4 */
      5
      6/*
      7 * The CFA-10055 is an expansion board for the CFA-10036 module and
      8 * CFA-10037, thus we need to include the CFA-10037 DTS.
      9 */
     10#include "imx28-cfa10037.dts"
     11
     12/ {
     13	model = "Crystalfontz CFA-10056 Board";
     14	compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
     15
     16	apb@80000000 {
     17		apbh@80000000 {
     18			pinctrl@80018000 {
     19				spi2_pins_cfa10056: spi2-cfa10056@0 {
     20					reg = <0>;
     21					fsl,pinmux-ids = <
     22						MX28_PAD_SSP2_SCK__GPIO_2_16
     23						MX28_PAD_SSP2_MOSI__GPIO_2_17
     24						MX28_PAD_SSP2_MISO__GPIO_2_18
     25						MX28_PAD_AUART1_TX__GPIO_3_5
     26					>;
     27					fsl,drive-strength = <MXS_DRIVE_8mA>;
     28					fsl,voltage = <MXS_VOLTAGE_HIGH>;
     29					fsl,pull-up = <MXS_PULL_ENABLE>;
     30				};
     31
     32				lcdif_pins_cfa10056: lcdif-10056@0 {
     33					reg = <0>;
     34					fsl,pinmux-ids = <
     35						MX28_PAD_LCD_RD_E__LCD_VSYNC
     36						MX28_PAD_LCD_WR_RWN__LCD_HSYNC
     37						MX28_PAD_LCD_RS__LCD_DOTCLK
     38						MX28_PAD_LCD_CS__LCD_ENABLE
     39					>;
     40					fsl,drive-strength = <MXS_DRIVE_4mA>;
     41					fsl,voltage = <MXS_VOLTAGE_HIGH>;
     42					fsl,pull-up = <MXS_PULL_DISABLE>;
     43				};
     44
     45				lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
     46					reg = <0>;
     47					fsl,pinmux-ids = <
     48						MX28_PAD_LCD_RESET__GPIO_3_30
     49					>;
     50					fsl,drive-strength = <MXS_DRIVE_4mA>;
     51					fsl,voltage = <MXS_VOLTAGE_HIGH>;
     52					fsl,pull-up = <MXS_PULL_ENABLE>;
     53				};
     54			};
     55
     56			lcdif@80030000 {
     57				pinctrl-names = "default";
     58				pinctrl-0 = <&lcdif_24bit_pins_a
     59						&lcdif_pins_cfa10056
     60						&lcdif_pins_cfa10056_pullup >;
     61				display = <&display0>;
     62				status = "okay";
     63
     64				display0: display0 {
     65					bits-per-pixel = <32>;
     66					bus-width = <24>;
     67
     68					display-timings {
     69						native-mode = <&timing0>;
     70						timing0: timing0 {
     71							clock-frequency = <32000000>;
     72							hactive = <480>;
     73							vactive = <800>;
     74							hback-porch = <2>;
     75							hfront-porch = <2>;
     76							vback-porch = <2>;
     77							vfront-porch = <2>;
     78							hsync-len = <5>;
     79							vsync-len = <5>;
     80							hsync-active = <0>;
     81							vsync-active = <0>;
     82							de-active = <1>;
     83							pixelclk-active = <1>;
     84						};
     85					};
     86				};
     87			};
     88		};
     89	};
     90
     91	spi2 {
     92		compatible = "spi-gpio";
     93		pinctrl-names = "default";
     94		pinctrl-0 = <&spi2_pins_cfa10056>;
     95		status = "okay";
     96		gpio-sck = <&gpio2 16 0>;
     97		gpio-mosi = <&gpio2 17 0>;
     98		gpio-miso = <&gpio2 18 0>;
     99		cs-gpios = <&gpio3 5 0>;
    100		num-chipselects = <1>;
    101		#address-cells = <1>;
    102		#size-cells = <0>;
    103
    104		hx8369: hx8369@0 {
    105			compatible = "himax,hx8369a", "himax,hx8369";
    106			reg = <0>;
    107			spi-max-frequency = <100000>;
    108			spi-cpol;
    109			spi-cpha;
    110			gpios-reset = <&gpio3 30 0>;
    111		};
    112	};
    113};