cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx31-lite.dts (3411B)

      1// SPDX-License-Identifier: GPL-2.0+
      2//
      3// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
      4
      5/dts-v1/;
      6
      7#include "imx31.dtsi"
      8
      9#include <dt-bindings/gpio/gpio.h>
     10#include <dt-bindings/interrupt-controller/irq.h>
     11
     12/ {
     13	model = "LogicPD i.MX31 Lite";
     14	compatible = "logicpd,imx31-lite", "fsl,imx31";
     15
     16	chosen {
     17		stdout-path = &uart1;
     18	};
     19
     20	memory@80000000 {
     21		device_type = "memory";
     22		reg = <0x80000000 0x8000000>;
     23	};
     24
     25	leds {
     26		compatible = "gpio-leds";
     27
     28		led0 {
     29			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
     30		};
     31
     32		led1 {
     33			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
     34		};
     35	};
     36};
     37
     38&ata {
     39	status = "okay";
     40};
     41
     42&nfc {
     43	nand-bus-width = <8>;
     44	nand-ecc-mode = "hw";
     45	nand-on-flash-bbt;
     46	status = "okay";
     47};
     48
     49&sdhci1 {
     50	bus-width = <4>;
     51	cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
     52	wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
     53	status = "okay";
     54};
     55
     56&spi2 {
     57	status = "okay";
     58
     59	pmic@0 {
     60		compatible = "fsl,mc13783";
     61		reg = <0>;
     62		spi-cs-high;
     63		spi-max-frequency = <1000000>;
     64		interrupt-parent = <&gpio1>;
     65		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
     66
     67		fsl,mc13xxx-uses-adc;
     68		fsl,mc13xxx-uses-rtc;
     69
     70		regulators {
     71			sw1a {		/* QVCC */
     72				regulator-min-microvolt = <1200000>;
     73				regulator-max-microvolt = <1500000>;
     74				regulator-always-on;
     75				regulator-boot-on;
     76			};
     77
     78			sw1b {		/* QVCC */
     79				regulator-min-microvolt = <1200000>;
     80				regulator-max-microvolt = <1500000>;
     81				regulator-always-on;
     82				regulator-boot-on;
     83			};
     84
     85			sw2a {		/* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */
     86				regulator-min-microvolt = <1800000>;
     87				regulator-max-microvolt = <1800000>;
     88				regulator-always-on;
     89				regulator-boot-on;
     90			};
     91
     92			sw2b {		/* NVCC10 */
     93				regulator-min-microvolt = <1800000>;
     94				regulator-max-microvolt = <1800000>;
     95				regulator-always-on;
     96				regulator-boot-on;
     97			};
     98
     99			violo {		/* NVCC1 and NVCC7 */
    100				regulator-min-microvolt = <1800000>;
    101				regulator-max-microvolt = <1800000>;
    102				regulator-always-on;
    103				regulator-boot-on;
    104			};
    105
    106			viohi {		/* VIOHI */
    107				regulator-min-microvolt = <2775000>;
    108				regulator-max-microvolt = <2775000>;
    109				regulator-always-on;
    110				regulator-boot-on;
    111			};
    112
    113			vaudio {	/* VAUDIO */
    114				regulator-min-microvolt = <2775000>;
    115				regulator-max-microvolt = <2775000>;
    116			};
    117
    118			vcam {		/* NVCC4 */
    119				regulator-min-microvolt = <2800000>;
    120				regulator-max-microvolt = <2800000>;
    121			};
    122
    123			vgen {		/* NVCC5 / NVCC8 and NVCC6 / NVCC9 */
    124				regulator-min-microvolt = <2775000>;
    125				regulator-max-microvolt = <2775000>;
    126				regulator-always-on;
    127				regulator-boot-on;
    128			};
    129
    130			vmmc2 {		/* NVCC3 */
    131				regulator-min-microvolt = <1600000>;
    132				regulator-max-microvolt = <3000000>;
    133				regulator-always-on;
    134				regulator-boot-on;
    135			};
    136		};
    137	};
    138};
    139
    140&uart1 {
    141	uart-has-rtscts;
    142	status = "okay";
    143};
    144
    145/* Routed to the extension board */
    146&uart2 {
    147	uart-has-rtscts;
    148	status = "okay";
    149};
    150
    151/* Routed to the extension board */
    152&uart3 {
    153	uart-has-rtscts;
    154	status = "okay";
    155};
    156
    157&weim {
    158	status = "okay";
    159
    160	nor@0,0 {
    161		compatible = "cfi-flash";
    162		reg = <0 0x0 0x200000>;
    163		bank-width = <2>;
    164		linux,mtd-name = "physmap-flash.0";
    165		fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>;
    166	};
    167
    168	ethernet@4,0 {
    169		compatible = "smsc,lan9117", "smsc,lan9115";
    170		reg = <4 0x0 0x100>;
    171		interrupt-parent = <&gpio1>;
    172		interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
    173		phy-mode = "mii";
    174		reg-io-width = <2>;
    175		smsc,irq-push-pull;
    176		fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>;
    177	};
    178};