cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx50-kobo-aura.dts (5777B)


      1// SPDX-License-Identifier: GPL-2.0+
      2// Copyright 2019 Jonathan Neuschäfer
      3//
      4// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
      5
      6/dts-v1/;
      7#include "imx50.dtsi"
      8#include <dt-bindings/input/input.h>
      9#include <dt-bindings/interrupt-controller/irq.h>
     10
     11/ {
     12	model = "Kobo Aura (N514)";
     13	compatible = "kobo,aura", "fsl,imx50";
     14
     15	chosen {
     16		stdout-path = "serial1:115200n8";
     17	};
     18
     19	memory@70000000 {
     20		device_type = "memory";
     21		reg = <0x70000000 0x10000000>;
     22	};
     23
     24	gpio-leds {
     25		compatible = "gpio-leds";
     26		pinctrl-names = "default";
     27		pinctrl-0 = <&pinctrl_leds>;
     28
     29		on {
     30			label = "kobo_aura:orange:on";
     31			gpios = <&gpio6 24 GPIO_ACTIVE_LOW>;
     32			panic-indicator;
     33		};
     34	};
     35
     36	gpio-keys {
     37		compatible = "gpio-keys";
     38		pinctrl-names = "default";
     39		pinctrl-0 = <&pinctrl_gpiokeys>;
     40
     41		power {
     42			label = "Power Button";
     43			gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
     44			linux,code = <KEY_POWER>;
     45		};
     46
     47		hallsensor {
     48			label = "Hallsensor";
     49			gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
     50			linux,code = <KEY_RESERVED>;
     51			linux,input-type = <EV_SW>;
     52		};
     53
     54		frontlight {
     55			label = "Frontlight";
     56			gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
     57			linux,code = <KEY_DISPLAYTOGGLE>;
     58		};
     59	};
     60
     61	sd2_pwrseq: pwrseq {
     62		compatible = "mmc-pwrseq-simple";
     63		pinctrl-names = "default";
     64		pinctrl-0 = <&pinctrl_sd2_reset>;
     65		reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
     66	};
     67
     68	sd2_vmmc: gpio-regulator {
     69		compatible = "regulator-gpio";
     70		pinctrl-names = "default";
     71		pinctrl-0 = <&pinctrl_sd2_vmmc>;
     72		regulator-name = "vmmc";
     73		states = <3300000 0>;
     74		regulator-min-microvolt = <3300000>;
     75		regulator-max-microvolt = <3300000>;
     76		enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>;
     77		startup-delay-us = <100000>;
     78	};
     79};
     80
     81&esdhc1 {
     82	pinctrl-names = "default";
     83	pinctrl-0 = <&pinctrl_sd1>;
     84	max-frequency = <50000000>;
     85	bus-width = <4>;
     86	cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
     87	disable-wp;
     88	status = "okay";
     89
     90	/* External µSD card */
     91};
     92
     93&esdhc2 {
     94	pinctrl-names = "default";
     95	pinctrl-0 = <&pinctrl_sd2>;
     96	bus-width = <4>;
     97	max-frequency = <50000000>;
     98	disable-wp;
     99	mmc-pwrseq = <&sd2_pwrseq>;
    100	vmmc-supply = <&sd2_vmmc>;
    101	status = "okay";
    102
    103	/* CyberTan WC121 SDIO WiFi (BCM43362) */
    104};
    105
    106&esdhc3 {
    107	pinctrl-names = "default";
    108	pinctrl-0 = <&pinctrl_sd3>;
    109	bus-width = <8>;
    110	non-removable;
    111	max-frequency = <50000000>;
    112	disable-wp;
    113	status = "okay";
    114
    115	/* Internal eMMC */
    116};
    117
    118&i2c1 {
    119	pinctrl-names = "default";
    120	pinctrl-0 = <&pinctrl_i2c1>;
    121	status = "okay";
    122
    123	touchscreen@15 {
    124		reg = <0x15>;
    125		compatible = "elan,ektf2132";
    126		pinctrl-names = "default";
    127		pinctrl-0 = <&pinctrl_ts>;
    128		power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
    129		interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>;
    130	};
    131};
    132
    133&i2c2 {
    134	pinctrl-names = "default";
    135	pinctrl-0 = <&pinctrl_i2c2>;
    136	status = "okay";
    137
    138	/* TODO: TPS65185 PMIC for E Ink at 0x68 */
    139};
    140
    141&i2c3 {
    142	pinctrl-names = "default";
    143	pinctrl-0 = <&pinctrl_i2c3>;
    144	status = "okay";
    145
    146	embedded-controller@43 {
    147		pinctrl-names = "default";
    148		pinctrl-0 = <&pinctrl_ec>;
    149		compatible = "netronix,ntxec";
    150		reg = <0x43>;
    151		system-power-controller;
    152		interrupts-extended = <&gpio4 11 IRQ_TYPE_EDGE_FALLING>;
    153		#pwm-cells = <2>;
    154	};
    155};
    156
    157&iomuxc {
    158	pinctrl_ec: ecgrp {
    159		fsl,pins = <
    160			MX50_PAD_CSPI_SS0__GPIO4_11		0x0	/* INT */
    161		>;
    162	};
    163
    164	pinctrl_gpiokeys: gpiokeysgrp {
    165		fsl,pins = <
    166			MX50_PAD_CSPI_MISO__GPIO4_10		0x0
    167			MX50_PAD_SD2_D7__GPIO5_15		0x0
    168			MX50_PAD_KEY_ROW0__GPIO4_1		0x0
    169		>;
    170	};
    171
    172	pinctrl_i2c1: i2c1grp {
    173		fsl,pins = <
    174			MX50_PAD_I2C1_SCL__I2C1_SCL		0x400001fd
    175			MX50_PAD_I2C1_SDA__I2C1_SDA		0x400001fd
    176		>;
    177	};
    178
    179	pinctrl_i2c2: i2c2grp {
    180		fsl,pins = <
    181			MX50_PAD_I2C2_SCL__I2C2_SCL		0x400001fd
    182			MX50_PAD_I2C2_SDA__I2C2_SDA		0x400001fd
    183		>;
    184	};
    185
    186	pinctrl_i2c3: i2c3grp {
    187		fsl,pins = <
    188			MX50_PAD_I2C3_SCL__I2C3_SCL		0x400001fd
    189			MX50_PAD_I2C3_SDA__I2C3_SDA		0x400001fd
    190		>;
    191	};
    192
    193	pinctrl_leds: ledsgrp {
    194		fsl,pins = <
    195			MX50_PAD_PWM1__GPIO6_24			0x0
    196		>;
    197	};
    198
    199	pinctrl_sd1: sd1grp {
    200		fsl,pins = <
    201			MX50_PAD_SD1_CMD__ESDHC1_CMD		0x1e4
    202			MX50_PAD_SD1_CLK__ESDHC1_CLK		0xd4
    203			MX50_PAD_SD1_D0__ESDHC1_DAT0		0x1d4
    204			MX50_PAD_SD1_D1__ESDHC1_DAT1		0x1d4
    205			MX50_PAD_SD1_D2__ESDHC1_DAT2		0x1d4
    206			MX50_PAD_SD1_D3__ESDHC1_DAT3		0x1d4
    207
    208			MX50_PAD_SD2_CD__GPIO5_17		0x0
    209		>;
    210	};
    211
    212	pinctrl_sd2: sd2grp {
    213		fsl,pins = <
    214			MX50_PAD_SD2_CMD__ESDHC2_CMD		0x1e4
    215			MX50_PAD_SD2_CLK__ESDHC2_CLK		0xd4
    216			MX50_PAD_SD2_D0__ESDHC2_DAT0		0x1d4
    217			MX50_PAD_SD2_D1__ESDHC2_DAT1		0x1d4
    218			MX50_PAD_SD2_D2__ESDHC2_DAT2		0x1d4
    219			MX50_PAD_SD2_D3__ESDHC2_DAT3		0x1d4
    220		>;
    221	};
    222
    223	pinctrl_sd2_reset: sd2-resetgrp {
    224		fsl,pins = <
    225			MX50_PAD_ECSPI2_MOSI__GPIO4_17		0x0
    226		>;
    227	};
    228
    229	pinctrl_sd2_vmmc: sd2-vmmcgrp {
    230		fsl,pins = <
    231			MX50_PAD_ECSPI1_SCLK__GPIO4_12		0x0
    232		>;
    233	};
    234
    235	pinctrl_sd3: sd3grp {
    236		fsl,pins = <
    237			MX50_PAD_SD3_CMD__ESDHC3_CMD		0x1e4
    238			MX50_PAD_SD3_CLK__ESDHC3_CLK		0xd4
    239			MX50_PAD_SD3_D0__ESDHC3_DAT0		0x1d4
    240			MX50_PAD_SD3_D1__ESDHC3_DAT1		0x1d4
    241			MX50_PAD_SD3_D2__ESDHC3_DAT2		0x1d4
    242			MX50_PAD_SD3_D3__ESDHC3_DAT3		0x1d4
    243			MX50_PAD_SD3_D4__ESDHC3_DAT4		0x1d4
    244			MX50_PAD_SD3_D5__ESDHC3_DAT5		0x1d4
    245			MX50_PAD_SD3_D6__ESDHC3_DAT6		0x1d4
    246			MX50_PAD_SD3_D7__ESDHC3_DAT7		0x1d4
    247		>;
    248	};
    249
    250	pinctrl_ts: tsgrp {
    251		fsl,pins = <
    252			MX50_PAD_CSPI_MOSI__GPIO4_9		0x0
    253			MX50_PAD_SD2_D5__GPIO5_13		0x0
    254		>;
    255	};
    256
    257	pinctrl_uart2: uart2grp {
    258		fsl,pins = <
    259			MX50_PAD_UART2_TXD__UART2_TXD_MUX	0x1e4
    260			MX50_PAD_UART2_RXD__UART2_RXD_MUX	0x1e4
    261		>;
    262	};
    263
    264	pinctrl_usbphy: usbphygrp {
    265		fsl,pins = <
    266			MX50_PAD_ECSPI2_SS0__GPIO4_19		0x0
    267		>;
    268	};
    269};
    270
    271&uart2 {
    272	pinctrl-names = "default";
    273	pinctrl-0 = <&pinctrl_uart2>;
    274	status = "okay";
    275};
    276
    277&usbotg {
    278	phy_type = "utmi_wide";
    279	dr_mode = "peripheral";
    280	status = "okay";
    281};
    282
    283&usbphy0 {
    284	pinctrl-names = "default";
    285	pinctrl-0 = <&pinctrl_usbphy>;
    286	vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
    287};