cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx53-m53.dtsi (2848B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
      4 */
      5
      6#include "imx53.dtsi"
      7
      8/ {
      9	model = "Aries/DENX M53";
     10	compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
     11
     12	memory@70000000 {
     13		device_type = "memory";
     14		reg = <0x70000000 0x20000000>,
     15		      <0xb0000000 0x20000000>;
     16	};
     17
     18	regulators {
     19		compatible = "simple-bus";
     20		#address-cells = <1>;
     21		#size-cells = <0>;
     22
     23		reg_3p2v: regulator@0 {
     24			compatible = "regulator-fixed";
     25			reg = <0>;
     26			regulator-name = "3P2V";
     27			regulator-min-microvolt = <3200000>;
     28			regulator-max-microvolt = <3200000>;
     29			regulator-always-on;
     30		};
     31
     32		reg_backlight: regulator@1 {
     33			compatible = "regulator-fixed";
     34			reg = <1>;
     35			regulator-name = "lcd-supply";
     36			regulator-min-microvolt = <3200000>;
     37			regulator-max-microvolt = <3200000>;
     38			regulator-always-on;
     39		};
     40	};
     41};
     42
     43&i2c2 {
     44	pinctrl-names = "default";
     45	pinctrl-0 = <&pinctrl_i2c2>;
     46	clock-frequency = <400000>;
     47	status = "okay";
     48
     49	touchscreen@41 {
     50		compatible = "st,stmpe610";
     51		reg = <0x41>;
     52		id = <0>;
     53		blocks = <0x5>;
     54		interrupts = <6 0x0>;
     55		interrupt-parent = <&gpio7>;
     56		irq-trigger = <0x1>;
     57
     58		stmpe_touchscreen {
     59			compatible = "st,stmpe-ts";
     60			st,sample-time = <4>;
     61			st,mod-12b = <1>;
     62			st,ref-sel = <0>;
     63			st,adc-freq = <1>;
     64			st,ave-ctrl = <3>;
     65			st,touch-det-delay = <3>;
     66			st,settling = <4>;
     67			st,fraction-z = <7>;
     68			st,i-drive = <1>;
     69		};
     70	};
     71
     72	eeprom: eeprom@50 {
     73		compatible = "atmel,24c128";
     74		reg = <0x50>;
     75		pagesize = <32>;
     76	};
     77
     78	rtc: rtc@68 {
     79		compatible = "st,m41t62";
     80		reg = <0x68>;
     81	};
     82};
     83
     84&iomuxc {
     85	pinctrl-names = "default";
     86	pinctrl-0 = <&pinctrl_hog>;
     87
     88	imx53-m53evk {
     89		pinctrl_hog: hoggrp {
     90			fsl,pins = <
     91				MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK	0x80000000
     92				MX53_PAD_EIM_EB3__GPIO2_31		0x80000000
     93				MX53_PAD_PATA_DA_0__GPIO7_6		0x80000000
     94			>;
     95		};
     96
     97		pinctrl_i2c2: i2c2grp {
     98			fsl,pins = <
     99				MX53_PAD_EIM_D16__I2C2_SDA		0xc0000000
    100				MX53_PAD_EIM_EB2__I2C2_SCL		0xc0000000
    101			>;
    102		};
    103
    104		pinctrl_nand: nandgrp {
    105			fsl,pins = <
    106				MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B	0x4
    107				MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B	0x4
    108				MX53_PAD_NANDF_CLE__EMI_NANDF_CLE	0x4
    109				MX53_PAD_NANDF_ALE__EMI_NANDF_ALE	0x4
    110				MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B	0xe0
    111				MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0	0xe0
    112				MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0	0x4
    113				MX53_PAD_PATA_DATA0__EMI_NANDF_D_0	0xa4
    114				MX53_PAD_PATA_DATA1__EMI_NANDF_D_1	0xa4
    115				MX53_PAD_PATA_DATA2__EMI_NANDF_D_2	0xa4
    116				MX53_PAD_PATA_DATA3__EMI_NANDF_D_3	0xa4
    117				MX53_PAD_PATA_DATA4__EMI_NANDF_D_4	0xa4
    118				MX53_PAD_PATA_DATA5__EMI_NANDF_D_5	0xa4
    119				MX53_PAD_PATA_DATA6__EMI_NANDF_D_6	0xa4
    120				MX53_PAD_PATA_DATA7__EMI_NANDF_D_7	0xa4
    121			>;
    122		};
    123	};
    124};
    125
    126&nfc {
    127	pinctrl-names = "default";
    128	pinctrl-0 = <&pinctrl_nand>;
    129	nand-bus-width = <8>;
    130	nand-ecc-mode = "hw";
    131	status = "okay";
    132};