cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

imx53-qsb-common.dtsi (8514B)


      1// SPDX-License-Identifier: GPL-2.0+
      2//
      3// Copyright 2011 Freescale Semiconductor, Inc.
      4// Copyright 2011 Linaro Ltd.
      5
      6#include "imx53.dtsi"
      7
      8/ {
      9	chosen {
     10		stdout-path = &uart1;
     11	};
     12
     13	memory@70000000 {
     14		device_type = "memory";
     15		reg = <0x70000000 0x20000000>,
     16		      <0xb0000000 0x20000000>;
     17	};
     18
     19	display0: disp0 {
     20		compatible = "fsl,imx-parallel-display";
     21		pinctrl-names = "default";
     22		pinctrl-0 = <&pinctrl_ipu_disp0>;
     23
     24		#address-cells = <1>;
     25		#size-cells = <0>;
     26		status = "disabled";
     27
     28		port@0 {
     29			reg = <0>;
     30
     31			display0_in: endpoint {
     32				remote-endpoint = <&ipu_di0_disp0>;
     33			};
     34		};
     35
     36		port@1 {
     37			reg = <1>;
     38
     39			display_out: endpoint {
     40				remote-endpoint = <&panel_in>;
     41			};
     42		};
     43	};
     44
     45	gpio-keys {
     46		compatible = "gpio-keys";
     47
     48		power {
     49			label = "Power Button";
     50			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
     51			linux,code = <KEY_POWER>;
     52		};
     53
     54		volume-up {
     55			label = "Volume Up";
     56			gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
     57			linux,code = <KEY_VOLUMEUP>;
     58			wakeup-source;
     59		};
     60
     61		volume-down {
     62			label = "Volume Down";
     63			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
     64			linux,code = <KEY_VOLUMEDOWN>;
     65			wakeup-source;
     66		};
     67	};
     68
     69	leds {
     70		compatible = "gpio-leds";
     71		pinctrl-names = "default";
     72		pinctrl-0 = <&led_pin_gpio7_7>;
     73
     74		user {
     75			label = "Heartbeat";
     76			gpios = <&gpio7 7 0>;
     77			linux,default-trigger = "heartbeat";
     78		};
     79	};
     80
     81	panel {
     82		compatible = "sii,43wvf1g";
     83
     84		port {
     85			panel_in: endpoint {
     86				remote-endpoint = <&display_out>;
     87			};
     88		};
     89	};
     90
     91	regulators {
     92		compatible = "simple-bus";
     93		#address-cells = <1>;
     94		#size-cells = <0>;
     95
     96		reg_3p2v: regulator@0 {
     97			compatible = "regulator-fixed";
     98			reg = <0>;
     99			regulator-name = "3P2V";
    100			regulator-min-microvolt = <3200000>;
    101			regulator-max-microvolt = <3200000>;
    102			regulator-always-on;
    103		};
    104
    105		reg_usb_vbus: regulator@1 {
    106			compatible = "regulator-fixed";
    107			reg = <1>;
    108			regulator-name = "usb_vbus";
    109			regulator-min-microvolt = <5000000>;
    110			regulator-max-microvolt = <5000000>;
    111			gpio = <&gpio7 8 0>;
    112			enable-active-high;
    113		};
    114	};
    115
    116	sound {
    117		compatible = "fsl,imx53-qsb-sgtl5000",
    118			     "fsl,imx-audio-sgtl5000";
    119		model = "imx53-qsb-sgtl5000";
    120		ssi-controller = <&ssi2>;
    121		audio-codec = <&sgtl5000>;
    122		audio-routing =
    123			"MIC_IN", "Mic Jack",
    124			"Mic Jack", "Mic Bias",
    125			"Headphone Jack", "HP_OUT";
    126		mux-int-port = <2>;
    127		mux-ext-port = <5>;
    128	};
    129};
    130
    131&cpu0 {
    132	/* CPU rated to 1GHz, not 1.2GHz as per the default settings */
    133	operating-points = <
    134		/* kHz   uV */
    135		166666  850000
    136		400000  900000
    137		800000  1050000
    138		1000000 1200000
    139	>;
    140};
    141
    142&esdhc1 {
    143	pinctrl-names = "default";
    144	pinctrl-0 = <&pinctrl_esdhc1>;
    145	cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
    146	status = "okay";
    147};
    148
    149&ipu_di0_disp0 {
    150	remote-endpoint = <&display0_in>;
    151};
    152
    153&ssi2 {
    154	status = "okay";
    155};
    156
    157&esdhc3 {
    158	pinctrl-names = "default";
    159	pinctrl-0 = <&pinctrl_esdhc3>;
    160	cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
    161	wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
    162	bus-width = <8>;
    163	status = "okay";
    164};
    165
    166&iomuxc {
    167	pinctrl-names = "default";
    168	pinctrl-0 = <&pinctrl_hog>;
    169
    170	imx53-qsb {
    171		pinctrl_hog: hoggrp {
    172			fsl,pins = <
    173				MX53_PAD_GPIO_8__GPIO1_8          0x80000000
    174				MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
    175				MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
    176				MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
    177				MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
    178				MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
    179				MX53_PAD_PATA_DA_2__GPIO7_8	  0x80000000
    180				MX53_PAD_GPIO_16__GPIO7_11        0x80000000
    181			>;
    182		};
    183
    184		led_pin_gpio7_7: led_gpio7_7 {
    185			fsl,pins = <
    186				MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
    187			>;
    188		};
    189
    190		pinctrl_audmux: audmuxgrp {
    191			fsl,pins = <
    192				MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC	0x80000000
    193				MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	0x80000000
    194				MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	0x80000000
    195				MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	0x80000000
    196			>;
    197		};
    198
    199		pinctrl_codec: codecgrp {
    200			fsl,pins = <
    201				MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK	0x1c4
    202			>;
    203		};
    204
    205		pinctrl_esdhc1: esdhc1grp {
    206			fsl,pins = <
    207				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
    208				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
    209				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
    210				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
    211				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
    212				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
    213				MX53_PAD_EIM_DA13__GPIO3_13		0xe4
    214			>;
    215		};
    216
    217		pinctrl_esdhc3: esdhc3grp {
    218			fsl,pins = <
    219				MX53_PAD_PATA_DATA8__ESDHC3_DAT0	0x1d5
    220				MX53_PAD_PATA_DATA9__ESDHC3_DAT1	0x1d5
    221				MX53_PAD_PATA_DATA10__ESDHC3_DAT2	0x1d5
    222				MX53_PAD_PATA_DATA11__ESDHC3_DAT3	0x1d5
    223				MX53_PAD_PATA_DATA0__ESDHC3_DAT4	0x1d5
    224				MX53_PAD_PATA_DATA1__ESDHC3_DAT5	0x1d5
    225				MX53_PAD_PATA_DATA2__ESDHC3_DAT6	0x1d5
    226				MX53_PAD_PATA_DATA3__ESDHC3_DAT7	0x1d5
    227				MX53_PAD_PATA_RESET_B__ESDHC3_CMD	0x1d5
    228				MX53_PAD_PATA_IORDY__ESDHC3_CLK		0x1d5
    229			>;
    230		};
    231
    232		pinctrl_fec: fecgrp {
    233			fsl,pins = <
    234				MX53_PAD_FEC_MDC__FEC_MDC		0x4
    235				MX53_PAD_FEC_MDIO__FEC_MDIO		0x1fc
    236				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x180
    237				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x180
    238				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x180
    239				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x180
    240				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x180
    241				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x4
    242				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x4
    243				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x4
    244			>;
    245		};
    246
    247		/* open drain */
    248		pinctrl_i2c1: i2c1grp {
    249			fsl,pins = <
    250				MX53_PAD_CSI0_DAT8__I2C1_SDA		0x400001ec
    251				MX53_PAD_CSI0_DAT9__I2C1_SCL		0x400001ec
    252			>;
    253		};
    254
    255		pinctrl_i2c2: i2c2grp {
    256			fsl,pins = <
    257				MX53_PAD_KEY_ROW3__I2C2_SDA		0xc0000000
    258				MX53_PAD_KEY_COL3__I2C2_SCL		0xc0000000
    259			>;
    260		};
    261
    262		pinctrl_ipu_disp0: ipudisp0grp {
    263			fsl,pins = <
    264				MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK	0x5
    265				MX53_PAD_DI0_PIN15__IPU_DI0_PIN15	0x5
    266				MX53_PAD_DI0_PIN2__IPU_DI0_PIN2		0x5
    267				MX53_PAD_DI0_PIN3__IPU_DI0_PIN3		0x5
    268				MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0	0x5
    269				MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1	0x5
    270				MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2	0x5
    271				MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3	0x5
    272				MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4	0x5
    273				MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5	0x5
    274				MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6	0x5
    275				MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7	0x5
    276				MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8	0x5
    277				MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9	0x5
    278				MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10	0x5
    279				MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11	0x5
    280				MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12	0x5
    281				MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13	0x5
    282				MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14	0x5
    283				MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15	0x5
    284				MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16	0x5
    285				MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17	0x5
    286				MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18	0x5
    287				MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19	0x5
    288				MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20	0x5
    289				MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21	0x5
    290				MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22	0x5
    291				MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23	0x5
    292			>;
    293		};
    294
    295		pinctrl_vga_sync: vgasync-grp {
    296			fsl,pins = <
    297				/* VGA_HSYNC, VSYNC with max drive strength */
    298				MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
    299				MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
    300			>;
    301		};
    302
    303		pinctrl_uart1: uart1grp {
    304			fsl,pins = <
    305				MX53_PAD_CSI0_DAT10__UART1_TXD_MUX	0x1e4
    306				MX53_PAD_CSI0_DAT11__UART1_RXD_MUX	0x1e4
    307			>;
    308		};
    309	};
    310};
    311
    312&tve {
    313	pinctrl-names = "default";
    314	pinctrl-0 = <&pinctrl_vga_sync>;
    315	ddc-i2c-bus = <&i2c2>;
    316	fsl,tve-mode = "vga";
    317	fsl,hsync-pin = <7>;	/* IPU DI1 PIN7 via EIM_OE */
    318	fsl,vsync-pin = <8>;	/* IPU DI1 PIN8 via EIM_RW */
    319	status = "okay";
    320};
    321
    322&uart1 {
    323	pinctrl-names = "default";
    324	pinctrl-0 = <&pinctrl_uart1>;
    325	status = "okay";
    326};
    327
    328&i2c2 {
    329	pinctrl-names = "default";
    330	pinctrl-0 = <&pinctrl_i2c2>;
    331	status = "okay";
    332
    333	sgtl5000: codec@a {
    334		compatible = "fsl,sgtl5000";
    335		reg = <0x0a>;
    336		pinctrl-names = "default";
    337		pinctrl-0 = <&pinctrl_codec>;
    338		#sound-dai-cells = <0>;
    339		VDDA-supply = <&reg_3p2v>;
    340		VDDIO-supply = <&reg_3p2v>;
    341		clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
    342	};
    343};
    344
    345&i2c1 {
    346	pinctrl-names = "default";
    347	pinctrl-0 = <&pinctrl_i2c1>;
    348	status = "okay";
    349
    350	accelerometer: mma8450@1c {
    351		compatible = "fsl,mma8450";
    352		reg = <0x1c>;
    353	};
    354};
    355
    356&audmux {
    357	pinctrl-names = "default";
    358	pinctrl-0 = <&pinctrl_audmux>;
    359	status = "okay";
    360};
    361
    362&fec {
    363	pinctrl-names = "default";
    364	pinctrl-0 = <&pinctrl_fec>;
    365	phy-mode = "rmii";
    366	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
    367	status = "okay";
    368};
    369
    370&sata {
    371	status = "okay";
    372};
    373
    374&vpu {
    375	status = "okay";
    376};
    377
    378&usbh1 {
    379	vbus-supply = <&reg_usb_vbus>;
    380	phy_type = "utmi";
    381	status = "okay";
    382};
    383
    384&usbotg {
    385	dr_mode = "peripheral";
    386	status = "okay";
    387};