cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx53-tx53-x13x.dts (6995B)


      1/*
      2 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
      3 *
      4 * This file is dual-licensed: you can use it either under the terms
      5 * of the GPL or the X11 license, at your option. Note that this dual
      6 * licensing only applies to this file, and not this project as a
      7 * whole.
      8 *
      9 *  a) This file is free software; you can redistribute it and/or
     10 *     modify it under the terms of the GNU General Public License
     11 *     version 2 as published by the Free Software Foundation.
     12 *
     13 *     This file is distributed in the hope that it will be useful,
     14 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 *     GNU General Public License for more details.
     17 *
     18 * Or, alternatively,
     19 *
     20 *  b) Permission is hereby granted, free of charge, to any person
     21 *     obtaining a copy of this software and associated documentation
     22 *     files (the "Software"), to deal in the Software without
     23 *     restriction, including without limitation the rights to use,
     24 *     copy, modify, merge, publish, distribute, sublicense, and/or
     25 *     sell copies of the Software, and to permit persons to whom the
     26 *     Software is furnished to do so, subject to the following
     27 *     conditions:
     28 *
     29 *     The above copyright notice and this permission notice shall be
     30 *     included in all copies or substantial portions of the Software.
     31 *
     32 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     33 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     34 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     35 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     36 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     37 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     38 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     39 *     OTHER DEALINGS IN THE SOFTWARE.
     40 * The code contained herein is licensed under the GNU General Public
     41 * License. You may obtain a copy of the GNU General Public License
     42 * Version 2 at the following locations:
     43 *
     44 * http://www.opensource.org/licenses/gpl-license.html
     45 * http://www.gnu.org/copyleft/gpl.html
     46 */
     47
     48/dts-v1/;
     49#include "imx53-tx53.dtsi"
     50#include <dt-bindings/input/input.h>
     51
     52/ {
     53	model = "Ka-Ro electronics TX53 module (LVDS)";
     54	compatible = "karo,tx53", "fsl,imx53";
     55
     56	aliases {
     57		display = &lvds0;
     58		lvds0 = &lvds0;
     59		lvds1 = &lvds1;
     60	};
     61
     62	backlight0: backlight0 {
     63		compatible = "pwm-backlight";
     64		pwms = <&pwm2 0 500000 0>;
     65		power-supply = <&reg_3v3>;
     66		brightness-levels = <
     67			  0  1  2  3  4  5  6  7  8  9
     68			 10 11 12 13 14 15 16 17 18 19
     69			 20 21 22 23 24 25 26 27 28 29
     70			 30 31 32 33 34 35 36 37 38 39
     71			 40 41 42 43 44 45 46 47 48 49
     72			 50 51 52 53 54 55 56 57 58 59
     73			 60 61 62 63 64 65 66 67 68 69
     74			 70 71 72 73 74 75 76 77 78 79
     75			 80 81 82 83 84 85 86 87 88 89
     76			 90 91 92 93 94 95 96 97 98 99
     77			100
     78		>;
     79		default-brightness-level = <50>;
     80	};
     81
     82	backlight1: backlight1 {
     83		compatible = "pwm-backlight";
     84		pwms = <&pwm1 0 500000 0>;
     85		power-supply = <&reg_3v3>;
     86		brightness-levels = <
     87			  0  1  2  3  4  5  6  7  8  9
     88			 10 11 12 13 14 15 16 17 18 19
     89			 20 21 22 23 24 25 26 27 28 29
     90			 30 31 32 33 34 35 36 37 38 39
     91			 40 41 42 43 44 45 46 47 48 49
     92			 50 51 52 53 54 55 56 57 58 59
     93			 60 61 62 63 64 65 66 67 68 69
     94			 70 71 72 73 74 75 76 77 78 79
     95			 80 81 82 83 84 85 86 87 88 89
     96			 90 91 92 93 94 95 96 97 98 99
     97			100
     98		>;
     99		default-brightness-level = <50>;
    100	};
    101
    102	reg_lcd_pwr0: regulator-lvds0-pwr {
    103		compatible = "regulator-fixed";
    104		regulator-name = "LVDS0 POWER";
    105		regulator-min-microvolt = <3300000>;
    106		regulator-max-microvolt = <3300000>;
    107		gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
    108		enable-active-high;
    109		regulator-boot-on;
    110	};
    111
    112	reg_lcd_pwr1: regulator-lvds1-pwr {
    113		compatible = "regulator-fixed";
    114		regulator-name = "LVDS1 POWER";
    115		regulator-min-microvolt = <3300000>;
    116		regulator-max-microvolt = <3300000>;
    117		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
    118		enable-active-high;
    119		regulator-boot-on;
    120	};
    121};
    122
    123&i2c3 {
    124	pinctrl-names = "default", "gpio";
    125	pinctrl-0 = <&pinctrl_i2c3>;
    126	pinctrl-1 = <&pinctrl_i2c3_gpio>;
    127	scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
    128	sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
    129	status = "okay";
    130
    131	sgtl5000: codec@a {
    132		compatible = "fsl,sgtl5000";
    133		reg = <0x0a>;
    134		#sound-dai-cells = <0>;
    135		VDDA-supply = <&reg_2v5>;
    136		VDDIO-supply = <&reg_3v3>;
    137		clocks = <&mclk>;
    138	};
    139};
    140
    141&iomuxc {
    142	imx53-tx53-x13x {
    143		pinctrl_lvds0: lvds0grp {
    144			fsl,pins = <
    145				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
    146				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
    147				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
    148				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
    149				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
    150			>;
    151		};
    152
    153		pinctrl_lvds1: lvds1grp {
    154			fsl,pins = <
    155				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
    156				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
    157				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
    158				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
    159				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
    160			>;
    161		};
    162
    163		pinctrl_pwm1: pwm1grp {
    164			fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
    165		};
    166
    167		pinctrl_eeti1: eeti1grp {
    168			fsl,pins = <
    169				MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
    170			>;
    171		};
    172
    173		pinctrl_eeti2: eeti2grp {
    174			fsl,pins = <
    175				MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
    176			>;
    177		};
    178	};
    179};
    180
    181&ldb {
    182	pinctrl-names = "default";
    183	pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
    184	status = "okay";
    185
    186	lvds0: lvds-channel@0 {
    187		fsl,data-mapping = "spwg";
    188		fsl,data-width = <18>;
    189		status = "okay";
    190
    191		display-timings {
    192			native-mode = <&lvds0_timing0>;
    193
    194			lvds0_timing0: hsd100pxn1 {
    195				clock-frequency = <65000000>;
    196				hactive = <1024>;
    197				vactive = <768>;
    198				hback-porch = <220>;
    199				hsync-len = <60>;
    200				hfront-porch = <40>;
    201				vback-porch = <21>;
    202				vsync-len = <10>;
    203				vfront-porch = <7>;
    204				hsync-active = <0>;
    205				vsync-active = <0>;
    206				de-active = <1>;
    207				pixelclk-active = <1>;
    208			};
    209
    210			lvds0_timing1: nl12880bc20 {
    211				clock-frequency = <71000000>;
    212				hactive = <1280>;
    213				vactive = <800>;
    214				hback-porch = <50>;
    215				hsync-len = <60>;
    216				hfront-porch = <50>;
    217				vback-porch = <5>;
    218				vsync-len = <13>;
    219				vfront-porch = <5>;
    220				hsync-active = <0>;
    221				vsync-active = <0>;
    222				de-active = <1>;
    223				pixelclk-active = <1>;
    224			};
    225		};
    226	};
    227
    228	lvds1: lvds-channel@1 {
    229		fsl,data-mapping = "spwg";
    230		fsl,data-width = <18>;
    231		status = "okay";
    232
    233		display-timings {
    234			native-mode = <&lvds1_timing0>;
    235
    236			lvds1_timing0: hsd100pxn1 {
    237				clock-frequency = <65000000>;
    238				hactive = <1024>;
    239				vactive = <768>;
    240				hback-porch = <220>;
    241				hsync-len = <60>;
    242				hfront-porch = <40>;
    243				vback-porch = <21>;
    244				vsync-len = <10>;
    245				vfront-porch = <7>;
    246				hsync-active = <0>;
    247				vsync-active = <0>;
    248				de-active = <1>;
    249				pixelclk-active = <1>;
    250			};
    251		};
    252	};
    253};
    254
    255&pwm1 {
    256	pinctrl-names = "default";
    257	pinctrl-0 = <&pinctrl_pwm1>;
    258};
    259
    260&sata {
    261	status = "okay";
    262};