cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx53-tx53.dtsi (15079B)


      1/*
      2 * Copyright 2012-2017 <LW@KARO-electronics.de>
      3 * based on imx53-qsb.dts
      4 *   Copyright 2011 Freescale Semiconductor, Inc.
      5 *   Copyright 2011 Linaro Ltd.
      6 *
      7 * This file is dual-licensed: you can use it either under the terms
      8 * of the GPL or the X11 license, at your option. Note that this dual
      9 * licensing only applies to this file, and not this project as a
     10 * whole.
     11 *
     12 *  a) This file is free software; you can redistribute it and/or
     13 *     modify it under the terms of the GNU General Public License
     14 *     version 2 as published by the Free Software Foundation.
     15 *
     16 *     This file is distributed in the hope that it will be useful,
     17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     19 *     GNU General Public License for more details.
     20 *
     21 * Or, alternatively,
     22 *
     23 *  b) Permission is hereby granted, free of charge, to any person
     24 *     obtaining a copy of this software and associated documentation
     25 *     files (the "Software"), to deal in the Software without
     26 *     restriction, including without limitation the rights to use,
     27 *     copy, modify, merge, publish, distribute, sublicense, and/or
     28 *     sell copies of the Software, and to permit persons to whom the
     29 *     Software is furnished to do so, subject to the following
     30 *     conditions:
     31 *
     32 *     The above copyright notice and this permission notice shall be
     33 *     included in all copies or substantial portions of the Software.
     34 *
     35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     42 *     OTHER DEALINGS IN THE SOFTWARE.
     43 */
     44
     45#include "imx53.dtsi"
     46#include <dt-bindings/gpio/gpio.h>
     47
     48/ {
     49	model = "Ka-Ro electronics TX53 module";
     50	compatible = "karo,tx53", "fsl,imx53";
     51
     52	/* Will be filled by the bootloader */
     53	memory@70000000 {
     54		device_type = "memory";
     55		reg = <0x70000000 0>;
     56	};
     57
     58	aliases {
     59		can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
     60		can1 = &can1;
     61		ipu = &ipu;
     62		reg-can-xcvr = &reg_can_xcvr;
     63		usbh1 = &usbh1;
     64		usbotg = &usbotg;
     65	};
     66
     67	clocks {
     68		ckih1 {
     69			clock-frequency = <0>;
     70		};
     71	};
     72
     73	mclk: clock-mclk {
     74		compatible = "fixed-clock";
     75		#clock-cells = <0>;
     76		clock-frequency = <26000000>;
     77	};
     78
     79	gpio-keys {
     80		compatible = "gpio-keys";
     81		pinctrl-names = "default";
     82		pinctrl-0 = <&pinctrl_gpio_key>;
     83
     84		power {
     85			label = "Power Button";
     86			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
     87			linux,code = <116>; /* KEY_POWER */
     88			wakeup-source;
     89		};
     90	};
     91
     92	leds {
     93		compatible = "gpio-leds";
     94		pinctrl-names = "default";
     95		pinctrl-0 = <&pinctrl_stk5led>;
     96
     97		user {
     98			label = "Heartbeat";
     99			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
    100			linux,default-trigger = "heartbeat";
    101		};
    102	};
    103
    104	reg_2v5: regulator-2v5 {
    105		compatible = "regulator-fixed";
    106		regulator-name = "2V5";
    107		regulator-min-microvolt = <2500000>;
    108		regulator-max-microvolt = <2500000>;
    109	};
    110
    111	reg_3v3: regulator-3v3 {
    112		compatible = "regulator-fixed";
    113		regulator-name = "3V3";
    114		regulator-min-microvolt = <3300000>;
    115		regulator-max-microvolt = <3300000>;
    116	};
    117
    118	reg_can_xcvr: regulator-can-xcvr {
    119		compatible = "regulator-fixed";
    120		regulator-name = "CAN XCVR";
    121		regulator-min-microvolt = <3300000>;
    122		regulator-max-microvolt = <3300000>;
    123		pinctrl-names = "default";
    124		pinctrl-0 = <&pinctrl_can_xcvr>;
    125		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
    126	};
    127
    128	reg_usbh1_vbus: regulator-usbh1-vbus {
    129		compatible = "regulator-fixed";
    130		regulator-name = "usbh1_vbus";
    131		regulator-min-microvolt = <5000000>;
    132		regulator-max-microvolt = <5000000>;
    133		pinctrl-names = "default";
    134		pinctrl-0 = <&pinctrl_usbh1_vbus>;
    135		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
    136		enable-active-high;
    137	};
    138
    139	reg_usbotg_vbus: regulator-usbotg-vbus {
    140		compatible = "regulator-fixed";
    141		regulator-name = "usbotg_vbus";
    142		regulator-min-microvolt = <5000000>;
    143		regulator-max-microvolt = <5000000>;
    144		pinctrl-names = "default";
    145		pinctrl-0 = <&pinctrl_usbotg_vbus>;
    146		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
    147		enable-active-high;
    148	};
    149
    150	sound {
    151		compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
    152		model = "tx53-audio-sgtl5000";
    153		ssi-controller = <&ssi1>;
    154		audio-codec = <&sgtl5000>;
    155		audio-routing =
    156			"MIC_IN", "Mic Jack",
    157			"Mic Jack", "Mic Bias",
    158			"Headphone Jack", "HP_OUT";
    159		/* '1' based port numbers according to datasheet names */
    160		mux-int-port = <1>;
    161		mux-ext-port = <5>;
    162	};
    163};
    164
    165&audmux {
    166	pinctrl-names = "default";
    167	pinctrl-0 = <&pinctrl_ssi1>;
    168	status = "okay";
    169};
    170
    171&can1 {
    172	pinctrl-names = "default";
    173	pinctrl-0 = <&pinctrl_can1>;
    174	xceiver-supply = <&reg_can_xcvr>;
    175	status = "okay";
    176};
    177
    178&can2 {
    179	pinctrl-names = "default";
    180	pinctrl-0 = <&pinctrl_can2>;
    181	xceiver-supply = <&reg_can_xcvr>;
    182	status = "okay";
    183};
    184
    185&ecspi1 {
    186	pinctrl-names = "default";
    187	pinctrl-0 = <&pinctrl_ecspi1>;
    188	status = "okay";
    189
    190	cs-gpios = <
    191		&gpio2 30 GPIO_ACTIVE_HIGH
    192		&gpio3 19 GPIO_ACTIVE_HIGH
    193	>;
    194
    195};
    196
    197&esdhc1 {
    198	cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
    199	fsl,wp-controller;
    200	pinctrl-names = "default";
    201	pinctrl-0 = <&pinctrl_esdhc1>;
    202	status = "okay";
    203};
    204
    205&esdhc2 {
    206	cd-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
    207	fsl,wp-controller;
    208	pinctrl-names = "default";
    209	pinctrl-0 = <&pinctrl_esdhc2>;
    210	status = "okay";
    211};
    212
    213&fec {
    214	pinctrl-names = "default";
    215	pinctrl-0 = <&pinctrl_fec>;
    216	phy-mode = "rmii";
    217	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
    218	phy-handle = <&phy0>;
    219	mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
    220	status = "okay";
    221
    222	mdio {
    223		#address-cells = <1>;
    224		#size-cells = <0>;
    225
    226		phy0: ethernet-phy@0 {
    227			reg = <0>;
    228			interrupt-parent = <&gpio2>;
    229			interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
    230			device_type = "ethernet-phy";
    231		};
    232	};
    233};
    234
    235&i2c1 {
    236	pinctrl-names = "default", "gpio";
    237	pinctrl-0 = <&pinctrl_i2c1>;
    238	pinctrl-0 = <&pinctrl_i2c1_gpio>;
    239	scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
    240	sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
    241	clock-frequency = <400000>;
    242	status = "okay";
    243
    244	rtc1: rtc@68 {
    245		compatible = "dallas,ds1339";
    246		reg = <0x68>;
    247		pinctrl-names = "default";
    248		pinctrl-0 = <&pinctrl_ds1339>;
    249		interrupt-parent = <&gpio4>;
    250		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
    251		trickle-resistor-ohms = <250>;
    252		trickle-diode-disable;
    253	};
    254};
    255
    256&iomuxc {
    257	pinctrl-names = "default";
    258	pinctrl-0 = <&pinctrl_hog>;
    259
    260	imx53-tx53 {
    261		pinctrl_hog: hoggrp {
    262			/* pins not in use by any device on the Starterkit board series */
    263			fsl,pins = <
    264				/* CMOS Sensor Interface */
    265				MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
    266				MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
    267				MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
    268				MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
    269				MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
    270				MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
    271				MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
    272				MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
    273				MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
    274				MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
    275				MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
    276				MX53_PAD_GPIO_0__GPIO1_0 0x1f4
    277				/* Module Specific Signal */
    278				/* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
    279				/* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
    280				MX53_PAD_EIM_D29__GPIO3_29 0x1f4
    281				MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
    282				/* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
    283				/* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
    284				MX53_PAD_EIM_A19__GPIO2_19 0x1f4
    285				MX53_PAD_EIM_A20__GPIO2_18 0x1f4
    286				MX53_PAD_EIM_A21__GPIO2_17 0x1f4
    287				MX53_PAD_EIM_A22__GPIO2_16 0x1f4
    288				MX53_PAD_EIM_A23__GPIO6_6 0x1f4
    289				MX53_PAD_EIM_A24__GPIO5_4 0x1f4
    290				MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
    291				MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
    292				MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
    293				MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
    294				/* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
    295				/* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
    296				MX53_PAD_GPIO_13__GPIO4_3 0x1f4
    297				MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
    298				MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
    299				MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
    300				MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
    301				MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
    302				MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
    303				MX53_PAD_EIM_OE__GPIO2_25 0x1f4
    304				MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
    305				MX53_PAD_EIM_RW__GPIO2_26 0x1f4
    306				MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
    307				MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
    308				MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
    309				MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
    310				MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
    311				MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
    312				MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
    313				MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
    314				>;
    315		};
    316
    317		pinctrl_can1: can1grp {
    318			fsl,pins = <
    319				MX53_PAD_GPIO_7__CAN1_TXCAN		0x80000000
    320				MX53_PAD_GPIO_8__CAN1_RXCAN		0x80000000
    321			>;
    322		};
    323
    324		pinctrl_can2: can2grp {
    325			fsl,pins = <
    326				MX53_PAD_KEY_COL4__CAN2_TXCAN		0x80000000
    327				MX53_PAD_KEY_ROW4__CAN2_RXCAN		0x80000000
    328			>;
    329		};
    330
    331		pinctrl_can_xcvr: can-xcvrgrp {
    332			fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
    333		};
    334
    335		pinctrl_ds1339: ds1339grp {
    336			fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
    337		};
    338
    339		pinctrl_ecspi1: ecspi1grp {
    340			fsl,pins = <
    341				MX53_PAD_GPIO_19__ECSPI1_RDY		0x80000000
    342				MX53_PAD_EIM_EB2__ECSPI1_SS0		0x80000000
    343				MX53_PAD_EIM_D16__ECSPI1_SCLK		0x80000000
    344				MX53_PAD_EIM_D17__ECSPI1_MISO		0x80000000
    345				MX53_PAD_EIM_D18__ECSPI1_MOSI		0x80000000
    346				MX53_PAD_EIM_D19__ECSPI1_SS1		0x80000000
    347			>;
    348		};
    349
    350		pinctrl_esdhc1: esdhc1grp {
    351			fsl,pins = <
    352				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
    353				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
    354				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
    355				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
    356				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
    357				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
    358				MX53_PAD_EIM_D24__GPIO3_24 0x1f0
    359			>;
    360		};
    361
    362		pinctrl_esdhc2: esdhc2grp {
    363			fsl,pins = <
    364				MX53_PAD_SD2_CMD__ESDHC2_CMD		0x1d5
    365				MX53_PAD_SD2_CLK__ESDHC2_CLK		0x1d5
    366				MX53_PAD_SD2_DATA0__ESDHC2_DAT0		0x1d5
    367				MX53_PAD_SD2_DATA1__ESDHC2_DAT1		0x1d5
    368				MX53_PAD_SD2_DATA2__ESDHC2_DAT2		0x1d5
    369				MX53_PAD_SD2_DATA3__ESDHC2_DAT3		0x1d5
    370				MX53_PAD_EIM_D25__GPIO3_25 0x1f0
    371			>;
    372		};
    373
    374		pinctrl_fec: fecgrp {
    375			fsl,pins = <
    376				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000
    377				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000
    378				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000
    379				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000
    380				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000
    381				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000
    382				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000
    383				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
    384				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000
    385				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000
    386			>;
    387		};
    388
    389		pinctrl_gpio_key: gpio-keygrp {
    390			fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
    391		};
    392
    393		pinctrl_i2c1: i2c1grp {
    394			fsl,pins = <
    395				MX53_PAD_EIM_D21__I2C1_SCL		0x400001e4
    396				MX53_PAD_EIM_D28__I2C1_SDA		0x400001e4
    397			>;
    398		};
    399
    400		pinctrl_i2c1_gpio: i2c1-gpiogrp {
    401			fsl,pins = <
    402				MX53_PAD_EIM_D21__GPIO3_21		0x400001e6
    403				MX53_PAD_EIM_D28__GPIO3_28		0x400001e6
    404			>;
    405		};
    406
    407		pinctrl_i2c3: i2c3grp {
    408			fsl,pins = <
    409				MX53_PAD_GPIO_3__I2C3_SCL		0x400001e4
    410				MX53_PAD_GPIO_6__I2C3_SDA		0x400001e4
    411			>;
    412		};
    413
    414		pinctrl_i2c3_gpio: i2c3-gpiogrp {
    415			fsl,pins = <
    416				MX53_PAD_GPIO_3__GPIO1_3		0x400001e6
    417				MX53_PAD_GPIO_6__GPIO1_6		0x400001e6
    418			>;
    419		};
    420
    421		pinctrl_nand: nandgrp {
    422			fsl,pins = <
    423				MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B	0x4
    424				MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B	0x4
    425				MX53_PAD_NANDF_CLE__EMI_NANDF_CLE	0x4
    426				MX53_PAD_NANDF_ALE__EMI_NANDF_ALE	0x4
    427				MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B	0xe0
    428				MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0	0xe0
    429				MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0	0x4
    430				MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0	0xa4
    431				MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1	0xa4
    432				MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2	0xa4
    433				MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3	0xa4
    434				MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4	0xa4
    435				MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5	0xa4
    436				MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6	0xa4
    437				MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7	0xa4
    438			>;
    439		};
    440
    441		pinctrl_pwm2: pwm2grp {
    442			fsl,pins = <
    443				MX53_PAD_GPIO_1__PWM2_PWMO		0x80000000
    444			>;
    445		};
    446
    447		pinctrl_ssi1: ssi1grp {
    448			fsl,pins = <
    449				MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC	0x80000000
    450				MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	0x80000000
    451				MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	0x80000000
    452				MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	0x80000000
    453			>;
    454		};
    455
    456		pinctrl_ssi2: ssi2grp {
    457			fsl,pins = <
    458				MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC	0x80000000
    459				MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD	0x80000000
    460				MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS	0x80000000
    461				MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD	0x80000000
    462				MX53_PAD_EIM_D27__GPIO3_27 0x1f0
    463			>;
    464		};
    465
    466		pinctrl_stk5led: stk5ledgrp {
    467			fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
    468		};
    469
    470		pinctrl_uart1: uart1grp {
    471			fsl,pins = <
    472				MX53_PAD_PATA_DIOW__UART1_TXD_MUX	0x1e4
    473				MX53_PAD_PATA_DMACK__UART1_RXD_MUX	0x1e4
    474				MX53_PAD_PATA_RESET_B__UART1_CTS	0x1c5
    475				MX53_PAD_PATA_IORDY__UART1_RTS		0x1c5
    476			>;
    477		};
    478
    479		pinctrl_uart2: uart2grp {
    480			fsl,pins = <
    481				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX	0x1c5
    482				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX	0x1c5
    483				MX53_PAD_PATA_DIOR__UART2_RTS		0x1c5
    484				MX53_PAD_PATA_INTRQ__UART2_CTS		0x1c5
    485			>;
    486		};
    487
    488		pinctrl_uart3: uart3grp {
    489			fsl,pins = <
    490				MX53_PAD_PATA_CS_0__UART3_TXD_MUX	0x1e4
    491				MX53_PAD_PATA_CS_1__UART3_RXD_MUX	0x1e4
    492				MX53_PAD_PATA_DA_1__UART3_CTS		0x1e4
    493				MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
    494			>;
    495		};
    496
    497		pinctrl_usbh1: usbh1grp {
    498			fsl,pins = <
    499				MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
    500			>;
    501		};
    502
    503		pinctrl_usbh1_vbus: usbh1-vbusgrp {
    504			fsl,pins = <
    505				MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
    506			>;
    507		};
    508
    509		pinctrl_usbotg_vbus: usbotg-vbusgrp {
    510			fsl,pins = <
    511				MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
    512				MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
    513			>;
    514		};
    515	};
    516};
    517
    518&ipu {
    519	status = "okay";
    520};
    521
    522&nfc {
    523	pinctrl-names = "default";
    524	pinctrl-0 = <&pinctrl_nand>;
    525	nand-bus-width = <8>;
    526	nand-ecc-mode = "hw";
    527	nand-on-flash-bbt;
    528	status = "okay";
    529};
    530
    531&pwm2 {
    532	pinctrl-names = "default";
    533	pinctrl-0 = <&pinctrl_pwm2>;
    534};
    535
    536&sdma {
    537	fsl,sdma-ram-script-name = "sdma-imx53.bin";
    538};
    539
    540&ssi1 {
    541	status = "okay";
    542};
    543
    544&ssi2 {
    545	status = "disabled";
    546};
    547
    548&uart1 {
    549	pinctrl-names = "default";
    550	pinctrl-0 = <&pinctrl_uart1>;
    551	uart-has-rtscts;
    552	status = "okay";
    553};
    554
    555&uart2 {
    556	pinctrl-names = "default";
    557	pinctrl-0 = <&pinctrl_uart2>;
    558	uart-has-rtscts;
    559	status = "okay";
    560};
    561
    562&uart3 {
    563	pinctrl-names = "default";
    564	pinctrl-0 = <&pinctrl_uart3>;
    565	uart-has-rtscts;
    566	status = "okay";
    567};
    568
    569&usbh1 {
    570	pinctrl-names = "default";
    571	pinctrl-0 = <&pinctrl_usbh1>;
    572	phy_type = "utmi";
    573	disable-over-current;
    574	vbus-supply = <&reg_usbh1_vbus>;
    575	status = "okay";
    576};
    577
    578&usbotg {
    579	phy_type = "utmi";
    580	dr_mode = "peripheral";
    581	disable-over-current;
    582	vbus-supply = <&reg_usbotg_vbus>;
    583	status = "okay";
    584};