cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6dl-colibri-eval-v3.dts (2768B)

      1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2/*
      3 * Copyright 2014-2022 Toradex
      4 * Copyright 2012 Freescale Semiconductor, Inc.
      5 * Copyright 2011 Linaro Ltd.
      6 */
      7
      8/dts-v1/;
      9
     10#include <dt-bindings/input/input.h>
     11#include <dt-bindings/interrupt-controller/irq.h>
     12#include "imx6dl.dtsi"
     13#include "imx6qdl-colibri.dtsi"
     14
     15/ {
     16	model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
     17	compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
     18		     "fsl,imx6dl";
     19
     20	aliases {
     21		i2c0 = &i2c2;
     22		i2c1 = &i2c3;
     23	};
     24
     25	aliases {
     26		rtc0 = &rtc_i2c;
     27		rtc1 = &snvs_rtc;
     28	};
     29
     30	chosen {
     31		stdout-path = "serial0:115200n8";
     32	};
     33
     34	/* Fixed crystal dedicated to mcp251x */
     35	clk16m: clock-16m {
     36		compatible = "fixed-clock";
     37		#clock-cells = <0>;
     38		clock-frequency = <16000000>;
     39		clock-output-names = "clk16m";
     40	};
     41};
     42
     43/* Colibri SSP */
     44&ecspi4 {
     45	status = "okay";
     46
     47	mcp251x0: mcp251x@0 {
     48		compatible = "microchip,mcp2515";
     49		clocks = <&clk16m>;
     50		interrupt-parent = <&gpio3>;
     51		interrupts = <27 0x2>;
     52		reg = <0>;
     53		spi-max-frequency = <10000000>;
     54		status = "okay";
     55	};
     56};
     57
     58/*
     59 * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
     60 */
     61&i2c3 {
     62	status = "okay";
     63
     64	/* M41T0M6 real time clock on carrier board */
     65	rtc_i2c: rtc@68 {
     66		compatible = "st,m41t0";
     67		reg = <0x68>;
     68	};
     69};
     70
     71&iomuxc {
     72	pinctrl-names = "default";
     73	pinctrl-0 = <
     74		&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
     75		&pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
     76		&pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
     77		&pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
     78	>;
     79};
     80
     81&pwm1 {
     82	status = "okay";
     83};
     84
     85&pwm2 {
     86	status = "okay";
     87};
     88
     89&pwm3 {
     90	status = "okay";
     91};
     92
     93&pwm4 {
     94	status = "okay";
     95};
     96
     97&reg_usb_host_vbus {
     98	status = "okay";
     99};
    100
    101&uart1 {
    102	status = "okay";
    103};
    104
    105&uart2 {
    106	status = "okay";
    107};
    108
    109&uart3 {
    110	status = "okay";
    111};
    112
    113&usbh1 {
    114	vbus-supply = <&reg_usb_host_vbus>;
    115	status = "okay";
    116};
    117
    118&usbotg {
    119	status = "okay";
    120};
    121
    122/* Colibri MMC */
    123&usdhc1 {
    124	status = "okay";
    125};
    126
    127&weim {
    128	status = "okay";
    129
    130	/* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */
    131	ranges = <0 0 0x08000000 0x02000000
    132		  1 0 0x0a000000 0x02000000
    133		  2 0 0x0c000000 0x02000000
    134		  3 0 0x0e000000 0x02000000>;
    135
    136	/* SRAM on Colibri nEXT_CS0 */
    137	sram@0,0 {
    138		compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
    139		reg = <0 0 0x00010000>;
    140		#address-cells = <1>;
    141		#size-cells = <1>;
    142		bank-width = <2>;
    143		fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
    144				      0x00000000 0x04000040 0x00000000>;
    145	};
    146
    147	/* SRAM on Colibri nEXT_CS1 */
    148	sram@1,0 {
    149		compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
    150		reg = <1 0 0x00010000>;
    151		#address-cells = <1>;
    152		#size-cells = <1>;
    153		bank-width = <2>;
    154		fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
    155				      0x00000000 0x04000040 0x00000000>;
    156	};
    157};