cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6dl-colibri-iris.dts (2558B)

      1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2/*
      3 * Copyright 2022 Toradex
      4 */
      5
      6/dts-v1/;
      7
      8#include <dt-bindings/input/input.h>
      9#include <dt-bindings/interrupt-controller/irq.h>
     10#include "imx6dl.dtsi"
     11#include "imx6qdl-colibri.dtsi"
     12
     13/ {
     14	model = "Toradex Colibri iMX6DL/S on Colibri Iris Board";
     15	compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl",
     16		     "fsl,imx6dl";
     17
     18	aliases {
     19		i2c0 = &i2c2;
     20		i2c1 = &i2c3;
     21	};
     22
     23	aliases {
     24		rtc0 = &rtc_i2c;
     25		rtc1 = &snvs_rtc;
     26	};
     27
     28	chosen {
     29		stdout-path = "serial0:115200n8";
     30	};
     31};
     32
     33/* Colibri SSP */
     34&ecspi4 {
     35	status = "okay";
     36};
     37
     38&gpio2 {
     39	pinctrl-names = "default";
     40	pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>;
     41
     42	/*
     43	 * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one
     44	 * wants to turn the transceiver off, that property has to be deleted
     45	 * and the gpio handled in userspace.
     46	 * The same applies to uart-b-c-on-x14-enable where the UART_B and
     47	 * UART_C transceiver is turned on.
     48	 */
     49	uart-a-on-x13-enable-hog {
     50		gpio-hog;
     51		gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
     52		output-high;
     53	};
     54
     55	uart-b-c-on-x14-enable-hog {
     56		gpio-hog;
     57		gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
     58		output-high;
     59	};
     60};
     61
     62/*
     63 * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
     64 */
     65&i2c3 {
     66	status = "okay";
     67
     68	rtc_i2c: rtc@68 {
     69		compatible = "st,m41t0";
     70		reg = <0x68>;
     71	};
     72};
     73
     74&iomuxc {
     75	pinctrl-names = "default";
     76	pinctrl-0 = <
     77		&pinctrl_gpio_iris
     78		&pinctrl_usbh_oc_1
     79		&pinctrl_usbc_id_1
     80	>;
     81
     82	pinctrl_gpio_iris: gpioirisgrp {
     83		fsl,pins = <
     84			MX6QDL_PAD_EIM_A17__GPIO2_IO21	0x1b0b0
     85			MX6QDL_PAD_EIM_A18__GPIO2_IO20	0x1b0b0
     86			MX6QDL_PAD_EIM_A19__GPIO2_IO19	0x1b0b0
     87			MX6QDL_PAD_EIM_A20__GPIO2_IO18	0x1b0b0
     88			MX6QDL_PAD_EIM_A23__GPIO6_IO06	0x1b0b0
     89			MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x1b0b0
     90			MX6QDL_PAD_NANDF_D3__GPIO2_IO03	0x1b0b0
     91			MX6QDL_PAD_SD2_DAT0__GPIO1_IO15	0x1b0b0
     92		>;
     93	};
     94
     95	pinctrl_uart1_forceoff: uart1forceoffgrp {
     96		fsl,pins = <
     97			MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
     98		>;
     99	};
    100
    101	pinctrl_uart23_forceoff: uart23forceoffgrp {
    102		fsl,pins = <
    103			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
    104		>;
    105	};
    106};
    107
    108&pwm1 {
    109	status = "okay";
    110};
    111
    112&pwm2 {
    113	status = "okay";
    114};
    115
    116&pwm3 {
    117	status = "okay";
    118};
    119
    120&pwm4 {
    121	status = "okay";
    122};
    123
    124&reg_usb_host_vbus {
    125	status = "okay";
    126};
    127
    128&uart1 {
    129	status = "okay";
    130};
    131
    132&uart2 {
    133	status = "okay";
    134};
    135
    136&uart3 {
    137	status = "okay";
    138};
    139
    140&usbh1 {
    141	vbus-supply = <&reg_usb_host_vbus>;
    142	status = "okay";
    143};
    144
    145&usbotg {
    146	status = "okay";
    147};
    148
    149/* Colibri MMC */
    150&usdhc1 {
    151	status = "okay";
    152};