cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6dl-skov-revc-lt6.dts (2832B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2//
      3// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
      4
      5/dts-v1/;
      6#include "imx6dl.dtsi"
      7#include "imx6qdl-skov-cpu.dtsi"
      8#include "imx6qdl-skov-cpu-revc.dtsi"
      9
     10/ {
     11	model = "SKOV IMX6 CPU SoloCore";
     12	compatible = "skov,imx6dl-skov-revc-lt6", "fsl,imx6dl";
     13
     14	backlight: backlight {
     15		compatible = "pwm-backlight";
     16		pinctrl-names = "default";
     17		pinctrl-0 = <&pinctrl_backlight>;
     18		enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;
     19		pwms = <&pwm2 0 20000 0>;
     20		brightness-levels = <0 255>;
     21		num-interpolated-steps = <17>;
     22		default-brightness-level = <8>;
     23		power-supply = <&reg_24v0>;
     24	};
     25
     26	display {
     27		compatible = "fsl,imx-parallel-display";
     28		pinctrl-names = "default";
     29		pinctrl-0 = <&pinctrl_ipu1>;
     30		#address-cells = <1>;
     31		#size-cells = <0>;
     32
     33		port@0 {
     34			reg = <0>;
     35
     36			display0_in: endpoint {
     37				remote-endpoint = <&ipu1_di0_disp0>;
     38			};
     39		};
     40
     41		port@1 {
     42			reg = <1>;
     43
     44			display0_out: endpoint {
     45				remote-endpoint = <&panel_in>;
     46			};
     47		};
     48	};
     49
     50	panel {
     51		compatible = "logictechno,lttd800480070-l6wh-rt";
     52		backlight = <&backlight>;
     53		power-supply = <&reg_3v3>;
     54
     55		port {
     56			panel_in: endpoint {
     57				remote-endpoint = <&display0_out>;
     58			};
     59		};
     60	};
     61};
     62
     63&ipu1_di0_disp0 {
     64	remote-endpoint = <&display0_in>;
     65};
     66
     67&iomuxc {
     68	pinctrl_backlight: backlightgrp {
     69		fsl,pins = <
     70			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23		0x58
     71		>;
     72	};
     73
     74	pinctrl_ipu1: ipu1grp {
     75		fsl,pins = <
     76			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
     77			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x10
     78			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
     79			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
     80			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
     81			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
     82			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
     83			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
     84			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
     85			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
     86			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
     87			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
     88			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
     89			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
     90			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
     91			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
     92			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
     93			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
     94			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
     95			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
     96			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
     97			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
     98			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
     99			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
    100			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
    101			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
    102			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
    103			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
    104		>;
    105	};
    106};