cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6q-b850v3.dts (5879B)


      1/*
      2 * Copyright 2015 Timesys Corporation.
      3 * Copyright 2015 General Electric Company
      4 *
      5 * This file is dual-licensed: you can use it either under the terms
      6 * of the GPL or the X11 license, at your option. Note that this dual
      7 * licensing only applies to this file, and not this project as a
      8 * whole.
      9 *
     10 *  a) This file is free software; you can redistribute it and/or
     11 *     modify it under the terms of the GNU General Public License
     12 *     version 2 as published by the Free Software Foundation.
     13 *
     14 *     This file is distributed in the hope that it will be useful,
     15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17 *     GNU General Public License for more details.
     18 *
     19 * Or, alternatively,
     20 *
     21 *  b) Permission is hereby granted, free of charge, to any person
     22 *     obtaining a copy of this software and associated documentation
     23 *     files (the "Software"), to deal in the Software without
     24 *     restriction, including without limitation the rights to use,
     25 *     copy, modify, merge, publish, distribute, sublicense, and/or
     26 *     sell copies of the Software, and to permit persons to whom the
     27 *     Software is furnished to do so, subject to the following
     28 *     conditions:
     29 *
     30 *     The above copyright notice and this permission notice shall be
     31 *     included in all copies or substantial portions of the Software.
     32 *
     33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     40 *     OTHER DEALINGS IN THE SOFTWARE.
     41 */
     42
     43/dts-v1/;
     44
     45#include "imx6q-bx50v3.dtsi"
     46
     47/ {
     48	model = "General Electric B850v3";
     49	compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
     50
     51	chosen {
     52		stdout-path = &uart3;
     53	};
     54};
     55
     56&ldb {
     57	fsl,dual-channel;
     58	status = "okay";
     59
     60	lvds0: lvds-channel@0 {
     61		fsl,data-mapping = "spwg";
     62		fsl,data-width = <24>;
     63		status = "okay";
     64
     65		port@4 {
     66			reg = <4>;
     67
     68			lvds0_out: endpoint {
     69				remote-endpoint = <&stdp4028_in>;
     70			};
     71		};
     72	};
     73};
     74
     75&i2c2 {
     76	pca9547_ddc: mux@70 {
     77		compatible = "nxp,pca9547";
     78		reg = <0x70>;
     79		#address-cells = <1>;
     80		#size-cells = <0>;
     81
     82		mux2_i2c1: i2c@0 {
     83			#address-cells = <1>;
     84			#size-cells = <0>;
     85			reg = <0x0>;
     86		};
     87
     88		mux2_i2c2: i2c@1 {
     89			#address-cells = <1>;
     90			#size-cells = <0>;
     91			reg = <0x1>;
     92		};
     93
     94		mux2_i2c3: i2c@2 {
     95			#address-cells = <1>;
     96			#size-cells = <0>;
     97			reg = <0x2>;
     98		};
     99
    100		mux2_i2c4: i2c@3 {
    101			#address-cells = <1>;
    102			#size-cells = <0>;
    103			reg = <0x3>;
    104		};
    105
    106		mux2_i2c5: i2c@4 {
    107			#address-cells = <1>;
    108			#size-cells = <0>;
    109			reg = <0x4>;
    110		};
    111
    112		mux2_i2c6: i2c@5 {
    113			#address-cells = <1>;
    114			#size-cells = <0>;
    115			reg = <0x5>;
    116		};
    117
    118		mux2_i2c7: i2c@6 {
    119			#address-cells = <1>;
    120			#size-cells = <0>;
    121			reg = <0x6>;
    122		};
    123
    124		mux2_i2c8: i2c@7 {
    125			#address-cells = <1>;
    126			#size-cells = <0>;
    127			reg = <0x7>;
    128		};
    129	};
    130};
    131
    132&hdmi {
    133	ddc-i2c-bus = <&mux2_i2c1>;
    134};
    135
    136&mux1_i2c1 {
    137	ads7830@4a {
    138		compatible = "ti,ads7830";
    139		reg = <0x4a>;
    140	};
    141};
    142
    143&mux2_i2c2 {
    144	clock-frequency = <100000>;
    145
    146	stdp2690@72 {
    147		compatible = "megachips,stdp2690-ge-b850v3-fw";
    148		reg = <0x72>;
    149
    150		ports {
    151			#address-cells = <1>;
    152			#size-cells = <0>;
    153
    154			port@0 {
    155				reg = <0>;
    156
    157				stdp2690_in: endpoint {
    158					remote-endpoint = <&stdp4028_out>;
    159				};
    160			};
    161
    162			port@1 {
    163				reg = <1>;
    164
    165				stdp2690_out: endpoint {
    166					/* Connector for external display */
    167				};
    168			};
    169		};
    170	};
    171
    172	stdp4028@73 {
    173		compatible = "megachips,stdp4028-ge-b850v3-fw";
    174		reg = <0x73>;
    175		interrupt-parent = <&gpio2>;
    176		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
    177
    178		ports {
    179			#address-cells = <1>;
    180			#size-cells = <0>;
    181
    182			port@0 {
    183				reg = <0>;
    184
    185				stdp4028_in: endpoint {
    186					remote-endpoint = <&lvds0_out>;
    187				};
    188			};
    189
    190			port@1 {
    191				reg = <1>;
    192
    193				stdp4028_out: endpoint {
    194					remote-endpoint = <&stdp2690_in>;
    195				};
    196			};
    197		};
    198	};
    199};
    200
    201&pca9539 {
    202	gpio-line-names = "AMB_P_INT1#", "AMB_P_INT2#", "BT_EN", "WLAN_EN",
    203			  "REMOTE_ON_PML#", "SM_D_ACT", "DP1_RST#", "DP2_RST#",
    204			  "", "", "", "",
    205			  "", "", "", "";
    206
    207	P10-hog {
    208		gpio-hog;
    209		gpios = <8 0>;
    210		output-low;
    211		line-name = "PCA9539-P10";
    212	};
    213
    214	P11-hog {
    215		gpio-hog;
    216		gpios = <9 0>;
    217		output-low;
    218		line-name = "PCA9539-P11";
    219	};
    220};
    221
    222&pci_root {
    223	/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
    224	bridge@1,0 {
    225		compatible = "pci10b5,8605";
    226		reg = <0x00010000 0 0 0 0>;
    227
    228		#address-cells = <3>;
    229		#size-cells = <2>;
    230		#interrupt-cells = <1>;
    231
    232		bridge@2,1 {
    233			compatible = "pci10b5,8605";
    234			reg = <0x00020800 0 0 0 0>;
    235
    236			#address-cells = <3>;
    237			#size-cells = <2>;
    238			#interrupt-cells = <1>;
    239
    240			/* Intel Corporation I210 Gigabit Network Connection */
    241			ethernet@3,0 {
    242				compatible = "pci8086,1533";
    243				reg = <0x00030000 0 0 0 0>;
    244			};
    245		};
    246
    247		bridge@2,2 {
    248			compatible = "pci10b5,8605";
    249			reg = <0x00021000 0 0 0 0>;
    250
    251			#address-cells = <3>;
    252			#size-cells = <2>;
    253			#interrupt-cells = <1>;
    254
    255			/* Intel Corporation I210 Gigabit Network Connection */
    256			switch_nic: ethernet@4,0 {
    257				compatible = "pci8086,1533";
    258				reg = <0x00040000 0 0 0 0>;
    259			};
    260		};
    261	};
    262};
    263
    264&switch_ports {
    265	port@0 {
    266		reg = <0>;
    267		label = "eneport1";
    268		phy-handle = <&switchphy0>;
    269	};
    270
    271	port@1 {
    272		reg = <1>;
    273		label = "eneport2";
    274		phy-handle = <&switchphy1>;
    275	};
    276
    277	port@2 {
    278		reg = <2>;
    279		label = "enix";
    280		phy-handle = <&switchphy2>;
    281	};
    282
    283	port@3 {
    284		reg = <3>;
    285		label = "enid";
    286		phy-handle = <&switchphy3>;
    287	};
    288
    289	port@4 {
    290		reg = <4>;
    291		label = "cpu";
    292		ethernet = <&switch_nic>;
    293		phy-handle = <&switchphy4>;
    294	};
    295};