cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6q-logicpd.dts (2758B)

      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (C) 2019 Logic PD, Inc.
      4
      5/dts-v1/;
      6#include "imx6q.dtsi"
      7#include "imx6-logicpd-som.dtsi"
      8#include "imx6-logicpd-baseboard.dtsi"
      9
     10/ {
     11	model = "Logic PD i.MX6QD SOM-M3";
     12	compatible = "logicpd,imx6q-logicpd", "fsl,imx6q";
     13
     14	backlight: backlight-lvds {
     15		compatible = "pwm-backlight";
     16		pwms = <&pwm3 0 20000 0>;
     17		brightness-levels = <0 4 8 16 32 64 128 255>;
     18		default-brightness-level = <6>;
     19		power-supply = <&reg_lcd>;
     20	};
     21
     22	panel-lvds0 {
     23		compatible = "okaya,rs800480t-7x0gp";
     24		power-supply = <&reg_lcd_reset>;
     25		backlight = <&backlight>;
     26
     27		port {
     28			panel_in_lvds0: endpoint {
     29				remote-endpoint = <&lvds0_out>;
     30			};
     31		};
     32	};
     33
     34	reg_lcd: regulator-lcd {
     35		pinctrl-names = "default";
     36		pinctrl-0 = <&pinctrl_lcd_reg>;
     37		compatible = "regulator-fixed";
     38		regulator-name = "lcd_panel_pwr";
     39		regulator-min-microvolt = <3300000>;
     40		regulator-max-microvolt = <3300000>;
     41		gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
     42		enable-active-high;
     43		vin-supply = <&reg_3v3>;
     44		startup-delay-us = <500000>;
     45	};
     46
     47	reg_lcd_reset: regulator-lcd-reset {
     48		pinctrl-names = "default";
     49		pinctrl-0 = <&pinctrl_lcd_reset>;
     50		compatible = "regulator-fixed";
     51		regulator-name = "nLCD_RESET";
     52		regulator-min-microvolt = <3300000>;
     53		regulator-max-microvolt = <3300000>;
     54		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
     55		enable-active-high;
     56		vin-supply = <&reg_lcd>;
     57	};
     58};
     59
     60&clks {
     61	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
     62			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
     63			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
     64			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
     65	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
     66				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
     67				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
     68				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
     69};
     70
     71&hdmi {
     72	ddc-i2c-bus = <&i2c3>;
     73	status = "okay";
     74};
     75
     76&i2c1 {
     77	touchscreen@26 {
     78		compatible = "ilitek,ili2117";
     79		reg = <0x26>;
     80		pinctrl-names = "default";
     81		pinctrl-0 = <&pinctrl_touchscreen>;
     82		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
     83	};
     84};
     85
     86&ldb {
     87	status = "okay";
     88
     89	lvds-channel@0 {
     90		fsl,data-mapping = "spwg";
     91		fsl,data-width = <24>;
     92		status = "okay";
     93
     94		port@4 {
     95			reg = <4>;
     96			lvds0_out: endpoint {
     97				remote-endpoint = <&panel_in_lvds0>;
     98			};
     99		};
    100	};
    101
    102};
    103
    104&pwm3 {
    105	status = "okay";
    106};
    107
    108&reg_hdmi {
    109	regulator-always-on;	/* Without this, the level shifter on HDMI doesn't turn on */
    110};
    111
    112&iomuxc {
    113	pinctrl_lcd_reg: lcdreg {
    114		fsl,pins = <
    115			MX6QDL_PAD_DI0_PIN15__GPIO4_IO17	0x100b0	/* R_LCD_PANEL_PWR */
    116		>;
    117	};
    118
    119	pinctrl_lcd_reset: lcdreset {
    120		fsl,pins = <
    121			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x100b0	/* LCD_nRESET */
    122		>;
    123	};
    124
    125	pinctrl_touchscreen: touchscreengrp {
    126		fsl,pins = <
    127			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x1b0b0	/* TOUCH_nPINTDAV */
    128		>;
    129	};
    130};