cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6q-sbc6x.dts (2095B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright 2013 Pavel Machek <pavel@denx.de>
      4 */
      5
      6/dts-v1/;
      7#include "imx6q.dtsi"
      8
      9/ {
     10	model = "MicroSys sbc6x board";
     11	compatible = "microsys,sbc6x", "fsl,imx6q";
     12
     13	memory@10000000 {
     14		device_type = "memory";
     15		reg = <0x10000000 0x80000000>;
     16	};
     17};
     18
     19
     20&fec {
     21	pinctrl-names = "default";
     22	pinctrl-0 = <&pinctrl_enet>;
     23	phy-mode = "rgmii";
     24	status = "okay";
     25};
     26
     27&iomuxc {
     28	imx6q-sbc6x {
     29		pinctrl_enet: enetgrp {
     30			fsl,pins = <
     31				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
     32				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
     33				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
     34				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
     35				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
     36				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
     37				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
     38				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
     39				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
     40				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
     41				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
     42				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
     43				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
     44				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
     45				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
     46				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
     47			>;
     48		};
     49
     50		pinctrl_uart1: uart1grp {
     51			fsl,pins = <
     52				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
     53				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
     54			>;
     55		};
     56
     57		pinctrl_usbotg: usbotggrp {
     58			fsl,pins = <
     59				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
     60			>;
     61		};
     62
     63		pinctrl_usdhc3: usdhc3grp {
     64			fsl,pins = <
     65				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
     66				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
     67				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
     68				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
     69				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
     70				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
     71			>;
     72		};
     73	};
     74};
     75
     76&uart1 {
     77	pinctrl-names = "default";
     78	pinctrl-0 = <&pinctrl_uart1>;
     79	status = "okay";
     80};
     81
     82&usbotg {
     83	pinctrl-names = "default";
     84	pinctrl-0 = <&pinctrl_usbotg>;
     85	disable-over-current;
     86	status = "okay";
     87};
     88
     89&usdhc3 {
     90	pinctrl-names = "default";
     91	pinctrl-0 = <&pinctrl_usdhc3>;
     92	status = "okay";
     93};