imx6qdl-colibri.dtsi (29876B)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "Toradex Colibri iMX6DL/S Module"; 12 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 13 14 backlight: backlight { 15 compatible = "pwm-backlight"; 16 brightness-levels = <0 127 191 223 239 247 251 255>; 17 default-brightness-level = <1>; 18 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 19 pinctrl-names = "default"; 20 pinctrl-0 = <&pinctrl_gpio_bl_on>; 21 power-supply = <®_module_3v3>; 22 pwms = <&pwm3 0 5000000>; 23 status = "disabled"; 24 }; 25 26 gpio-keys { 27 compatible = "gpio-keys"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_gpio_keys>; 30 31 wakeup { 32 debounce-interval = <10>; 33 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ 34 label = "Wake-Up"; 35 linux,code = <KEY_WAKEUP>; 36 wakeup-source; 37 }; 38 }; 39 40 lcd_display: disp0 { 41 compatible = "fsl,imx-parallel-display"; 42 interface-pix-fmt = "bgr666"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 45 status = "disabled"; 46 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 port@0 { 51 reg = <0>; 52 53 lcd_display_in: endpoint { 54 remote-endpoint = <&ipu1_di0_disp0>; 55 }; 56 }; 57 58 port@1 { 59 reg = <1>; 60 61 lcd_display_out: endpoint { 62 remote-endpoint = <&lcd_panel_in>; 63 }; 64 }; 65 }; 66 67 /* Will be filled by the bootloader */ 68 memory@10000000 { 69 device_type = "memory"; 70 reg = <0x10000000 0>; 71 }; 72 73 panel_dpi: panel-dpi { 74 /* 75 * edt,et057090dhu: EDT 5.7" LCD TFT 76 * edt,et070080dh6: EDT 7.0" LCD TFT 77 */ 78 compatible = "edt,et057090dhu"; 79 backlight = <&backlight>; 80 status = "disabled"; 81 82 port { 83 lcd_panel_in: endpoint { 84 remote-endpoint = <&lcd_display_out>; 85 }; 86 }; 87 }; 88 89 reg_module_3v3: regulator-module-3v3 { 90 compatible = "regulator-fixed"; 91 regulator-name = "+V3.3"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 regulator-always-on; 95 }; 96 97 reg_module_3v3_audio: regulator-module-3v3-audio { 98 compatible = "regulator-fixed"; 99 regulator-name = "+V3.3_AUDIO"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 regulator-always-on; 103 }; 104 105 reg_usb_host_vbus: regulator-usb-host-vbus { 106 compatible = "regulator-fixed"; 107 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 110 regulator-max-microvolt = <5000000>; 111 regulator-min-microvolt = <5000000>; 112 regulator-name = "usb_host_vbus"; 113 status = "disabled"; 114 }; 115 116 sound { 117 compatible = "fsl,imx-audio-sgtl5000"; 118 audio-codec = <&codec>; 119 audio-routing = 120 "Headphone Jack", "HP_OUT", 121 "LINE_IN", "Line In Jack", 122 "MIC_IN", "Mic Jack", 123 "Mic Jack", "Mic Bias"; 124 model = "imx6dl-colibri-sgtl5000"; 125 mux-int-port = <1>; 126 mux-ext-port = <5>; 127 ssi-controller = <&ssi1>; 128 }; 129 130 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 131 sound_spdif: sound-spdif { 132 compatible = "fsl,imx-audio-spdif"; 133 spdif-controller = <&spdif>; 134 spdif-in; 135 spdif-out; 136 model = "imx-spdif"; 137 status = "disabled"; 138 }; 139}; 140 141&audmux { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 144 status = "okay"; 145}; 146 147/* Optional on SODIMM 55/63 */ 148&can1 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_flexcan1>; 151 status = "disabled"; 152}; 153 154/* Optional on SODIMM 178/188 */ 155&can2 { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_flexcan2>; 158 status = "disabled"; 159}; 160 161&clks { 162 fsl,pmic-stby-poweroff; 163}; 164 165/* Colibri SSP */ 166&ecspi4 { 167 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_ecspi4>; 170 status = "disabled"; 171}; 172 173&fec { 174 phy-mode = "rmii"; 175 phy-handle = <ðphy>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_enet>; 178 status = "okay"; 179 180 mdio { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 ethphy: ethernet-phy@0 { 185 reg = <0>; 186 micrel,led-mode = <0>; 187 }; 188 }; 189}; 190 191&gpio1 { 192 gpio-line-names = "", 193 "SODIMM_67", 194 "SODIMM_180", 195 "SODIMM_196", 196 "SODIMM_174", 197 "SODIMM_176", 198 "SODIMM_194", 199 "SODIMM_55", 200 "SODIMM_63", 201 "SODIMM_28", 202 "SODIMM_93", 203 "SODIMM_69", 204 "SODIMM_99", 205 "SODIMM_130", 206 "SODIMM_106", 207 "SODIMM_98", 208 "SODIMM_192", 209 "SODIMM_49", 210 "SODIMM_190", 211 "SODIMM_51", 212 "SODIMM_47", 213 "SODIMM_53", 214 "", 215 "SODIMM_22"; 216}; 217 218&gpio2 { 219 gpio-line-names = "SODIMM_132", 220 "SODIMM_134", 221 "SODIMM_135", 222 "SODIMM_133", 223 "SODIMM_102", 224 "SODIMM_43", 225 "SODIMM_127", 226 "SODIMM_37", 227 "SODIMM_104", 228 "SODIMM_59", 229 "SODIMM_30", 230 "SODIMM_100", 231 "SODIMM_38", 232 "SODIMM_34", 233 "SODIMM_32", 234 "SODIMM_36", 235 "SODIMM_59", 236 "SODIMM_67", 237 "SODIMM_97", 238 "SODIMM_79", 239 "SODIMM_103", 240 "SODIMM_101", 241 "SODIMM_45", 242 "SODIMM_105", 243 "SODIMM_107", 244 "SODIMM_91", 245 "SODIMM_89", 246 "SODIMM_150", 247 "SODIMM_126", 248 "SODIMM_128", 249 "", 250 "SODIMM_94"; 251}; 252 253&gpio3 { 254 gpio-line-names = "SODIMM_111", 255 "SODIMM_113", 256 "SODIMM_115", 257 "SODIMM_117", 258 "SODIMM_119", 259 "SODIMM_121", 260 "SODIMM_123", 261 "SODIMM_125", 262 "SODIMM_110", 263 "SODIMM_112", 264 "SODIMM_114", 265 "SODIMM_116", 266 "SODIMM_118", 267 "SODIMM_120", 268 "SODIMM_122", 269 "SODIMM_124", 270 "", 271 "SODIMM_96", 272 "SODIMM_77", 273 "SODIMM_25", 274 "SODIMM_27", 275 "SODIMM_88", 276 "SODIMM_90", 277 "SODIMM_31", 278 "SODIMM_23", 279 "SODIMM_29", 280 "SODIMM_71", 281 "SODIMM_73", 282 "SODIMM_92", 283 "SODIMM_81", 284 "SODIMM_131", 285 "SODIMM_129"; 286}; 287 288&gpio4 { 289 gpio-line-names = "", 290 "", 291 "", 292 "", 293 "", 294 "SODIMM_168", 295 "", 296 "", 297 "", 298 "", 299 "SODIMM_184", 300 "SODIMM_186", 301 "HDMI_15", 302 "HDMI_16", 303 "SODIMM_178", 304 "SODIMM_188", 305 "SODIMM_56", 306 "SODIMM_44", 307 "SODIMM_68", 308 "SODIMM_82", 309 "SODIMM_24", 310 "SODIMM_76", 311 "SODIMM_70", 312 "SODIMM_60", 313 "SODIMM_58", 314 "SODIMM_78", 315 "SODIMM_72", 316 "SODIMM_80", 317 "SODIMM_46", 318 "SODIMM_62", 319 "SODIMM_48", 320 "SODIMM_74"; 321}; 322 323&gpio5 { 324 gpio-line-names = "SODIMM_95", 325 "", 326 "SODIMM_86", 327 "", 328 "SODIMM_65", 329 "SODIMM_50", 330 "SODIMM_52", 331 "SODIMM_54", 332 "SODIMM_66", 333 "SODIMM_64", 334 "SODIMM_57", 335 "SODIMM_61", 336 "SODIMM_136", 337 "SODIMM_138", 338 "SODIMM_140", 339 "SODIMM_142", 340 "SODIMM_144", 341 "SODIMM_146", 342 "SODIMM_172", 343 "SODIMM_170", 344 "SODIMM_149", 345 "SODIMM_151", 346 "SODIMM_153", 347 "SODIMM_155", 348 "SODIMM_157", 349 "SODIMM_159", 350 "SODIMM_161", 351 "SODIMM_163", 352 "SODIMM_33", 353 "SODIMM_35", 354 "SODIMM_165", 355 "SODIMM_167"; 356}; 357 358&gpio6 { 359 gpio-line-names = "SODIMM_169", 360 "SODIMM_171", 361 "SODIMM_173", 362 "SODIMM_175", 363 "SODIMM_177", 364 "SODIMM_179", 365 "SODIMM_85", 366 "SODIMM_166", 367 "SODIMM_160", 368 "SODIMM_162", 369 "SODIMM_158", 370 "SODIMM_164", 371 "", 372 "", 373 "SODIMM_156", 374 "SODIMM_75", 375 "SODIMM_154", 376 "", 377 "", 378 "", 379 "", 380 "", 381 "", 382 "", 383 "", 384 "", 385 "", 386 "", 387 "", 388 "", 389 "", 390 "SODIMM_152"; 391}; 392 393&gpio7 { 394 gpio-line-names = "", 395 "", 396 "", 397 "", 398 "", 399 "", 400 "", 401 "", 402 "", 403 "SODIMM_19", 404 "SODIMM_21", 405 "", 406 "SODIMM_137"; 407}; 408 409&hdmi { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_hdmi_ddc>; 412 status = "disabled"; 413}; 414 415/* 416 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 417 * touch screen controller 418 */ 419&i2c2 { 420 clock-frequency = <100000>; 421 pinctrl-names = "default", "gpio"; 422 pinctrl-0 = <&pinctrl_i2c2>; 423 pinctrl-1 = <&pinctrl_i2c2_gpio>; 424 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 425 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 426 status = "okay"; 427 428 pmic: pmic@8 { 429 compatible = "fsl,pfuze100"; 430 fsl,pmic-stby-poweroff; 431 reg = <0x08>; 432 433 regulators { 434 sw1a_reg: sw1ab { 435 regulator-always-on; 436 regulator-boot-on; 437 regulator-max-microvolt = <1875000>; 438 regulator-min-microvolt = <300000>; 439 regulator-ramp-delay = <6250>; 440 }; 441 442 sw1c_reg: sw1c { 443 regulator-always-on; 444 regulator-boot-on; 445 regulator-max-microvolt = <1875000>; 446 regulator-min-microvolt = <300000>; 447 regulator-ramp-delay = <6250>; 448 }; 449 450 sw3a_reg: sw3a { 451 regulator-always-on; 452 regulator-boot-on; 453 regulator-max-microvolt = <1975000>; 454 regulator-min-microvolt = <400000>; 455 }; 456 457 swbst_reg: swbst { 458 regulator-always-on; 459 regulator-boot-on; 460 regulator-max-microvolt = <5150000>; 461 regulator-min-microvolt = <5000000>; 462 }; 463 464 snvs_reg: vsnvs { 465 regulator-always-on; 466 regulator-boot-on; 467 regulator-max-microvolt = <3000000>; 468 regulator-min-microvolt = <1000000>; 469 }; 470 471 vref_reg: vrefddr { 472 regulator-always-on; 473 regulator-boot-on; 474 }; 475 476 /* vgen1: unused */ 477 478 vgen2_reg: vgen2 { 479 regulator-always-on; 480 regulator-boot-on; 481 regulator-max-microvolt = <1550000>; 482 regulator-min-microvolt = <800000>; 483 }; 484 485 /* 486 * +V3.3_1.8_SD1 coming off VGEN3 and supplying 487 * the i.MX 6 NVCC_SD1. 488 */ 489 vgen3_reg: vgen3 { 490 regulator-always-on; 491 regulator-boot-on; 492 regulator-max-microvolt = <3300000>; 493 regulator-min-microvolt = <1800000>; 494 }; 495 496 vgen4_reg: vgen4 { 497 regulator-always-on; 498 regulator-boot-on; 499 regulator-max-microvolt = <1800000>; 500 regulator-min-microvolt = <1800000>; 501 }; 502 503 vgen5_reg: vgen5 { 504 regulator-always-on; 505 regulator-boot-on; 506 regulator-max-microvolt = <3300000>; 507 regulator-min-microvolt = <1800000>; 508 }; 509 510 vgen6_reg: vgen6 { 511 regulator-always-on; 512 regulator-boot-on; 513 regulator-max-microvolt = <3300000>; 514 regulator-min-microvolt = <1800000>; 515 }; 516 }; 517 }; 518 519 codec: sgtl5000@a { 520 compatible = "fsl,sgtl5000"; 521 clocks = <&clks IMX6QDL_CLK_CKO>; 522 lrclk-strength = <3>; 523 reg = <0x0a>; 524 #sound-dai-cells = <0>; 525 VDDA-supply = <®_module_3v3_audio>; 526 VDDIO-supply = <®_module_3v3>; 527 VDDD-supply = <&vgen4_reg>; 528 }; 529 530 /* STMPE811 touch screen controller */ 531 stmpe811@41 { 532 compatible = "st,stmpe811"; 533 blocks = <0x5>; 534 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 535 interrupt-parent = <&gpio6>; 536 interrupt-controller; 537 id = <0>; 538 irq-trigger = <0x1>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&pinctrl_touch_int>; 541 reg = <0x41>; 542 /* 3.25 MHz ADC clock speed */ 543 st,adc-freq = <1>; 544 /* 12-bit ADC */ 545 st,mod-12b = <1>; 546 /* internal ADC reference */ 547 st,ref-sel = <0>; 548 /* ADC converstion time: 80 clocks */ 549 st,sample-time = <4>; 550 551 stmpe_ts: stmpe_touchscreen { 552 compatible = "st,stmpe-ts"; 553 /* 8 sample average control */ 554 st,ave-ctrl = <3>; 555 /* 7 length fractional part in z */ 556 st,fraction-z = <7>; 557 /* 558 * 50 mA typical 80 mA max touchscreen drivers 559 * current limit value 560 */ 561 st,i-drive = <1>; 562 /* 1 ms panel driver settling time */ 563 st,settling = <3>; 564 /* 5 ms touch detect interrupt delay */ 565 st,touch-det-delay = <5>; 566 status = "disabled"; 567 }; 568 569 stmpe_adc: stmpe_adc { 570 compatible = "st,stmpe-adc"; 571 /* forbid to use ADC channels 3-0 (touch) */ 572 st,norequest-mask = <0x0F>; 573 }; 574 }; 575}; 576 577/* 578 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 579 */ 580&i2c3 { 581 clock-frequency = <100000>; 582 pinctrl-names = "default", "gpio"; 583 pinctrl-0 = <&pinctrl_i2c3>; 584 pinctrl-1 = <&pinctrl_i2c3_gpio>; 585 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 586 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 587 status = "disabled"; 588 589 atmel_mxt_ts: touchscreen@4a { 590 compatible = "atmel,maxtouch"; 591 interrupt-parent = <&gpio2>; 592 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pinctrl_atmel_conn>; 595 reg = <0x4a>; 596 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ 597 status = "disabled"; 598 }; 599}; 600 601&ipu1_di0_disp0 { 602 remote-endpoint = <&lcd_display_in>; 603}; 604 605/* Colibri PWM<B> */ 606&pwm1 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_pwm1>; 609 status = "disabled"; 610}; 611 612/* Colibri PWM<D> */ 613&pwm2 { 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_pwm2>; 616 status = "disabled"; 617}; 618 619/* Colibri PWM<A> */ 620&pwm3 { 621 #pwm-cells = <2>; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pinctrl_pwm3>; 624 status = "disabled"; 625}; 626 627/* Colibri PWM<C> */ 628&pwm4 { 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pinctrl_pwm4>; 631 status = "disabled"; 632}; 633 634/* Optional S/PDIF out on SODIMM 137 */ 635&spdif { 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_spdif>; 638 status = "disabled"; 639}; 640 641&ssi1 { 642 status = "okay"; 643}; 644 645/* Colibri UART_A */ 646&uart1 { 647 fsl,dte-mode; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 650 uart-has-rtscts; 651 status = "disabled"; 652}; 653 654/* Colibri UART_B */ 655&uart2 { 656 fsl,dte-mode; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_uart2_dte>; 659 uart-has-rtscts; 660 status = "disabled"; 661}; 662 663/* Colibri UART_C */ 664&uart3 { 665 fsl,dte-mode; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_uart3_dte>; 668 status = "disabled"; 669}; 670 671&usbotg { 672 disable-over-current; 673 dr_mode = "peripheral"; 674 status = "disabled"; 675}; 676 677/* Colibri MMC */ 678&usdhc1 { 679 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 680 bus-width = <4>; 681 no-1-8-v; 682 disable-wp; 683 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 684 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 685 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; 686 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; 687 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; 688 vmmc-supply = <®_module_3v3>; 689 vqmmc-supply = <&vgen3_reg>; 690 status = "disabled"; 691}; 692 693/* eMMC */ 694&usdhc3 { 695 bus-width = <8>; 696 no-1-8-v; 697 non-removable; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_usdhc3>; 700 vqmmc-supply = <®_module_3v3>; 701 status = "okay"; 702}; 703 704&weim { 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 707 &pinctrl_weim_cs1 &pinctrl_weim_cs2 708 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 709 #address-cells = <2>; 710 #size-cells = <1>; 711 status = "disabled"; 712}; 713 714&iomuxc { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_usbh_oc_1>; 717 718 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 719 /* NOTE: This pin group conflicts with pin groups 720 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. 721 */ 722 pinctrl_atmel_adap: atmeladaptergrp { 723 fsl,pins = < 724 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ 725 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ 726 >; 727 }; 728 729 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 730 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and 731 * pinctrl_weim_cs2. Don't use them simultaneously. 732 */ 733 pinctrl_atmel_conn: atmelconnectorgrp { 734 fsl,pins = < 735 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ 736 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ 737 >; 738 }; 739 740 pinctrl_audmux: audmuxgrp { 741 fsl,pins = < 742 /* SGTL5000 sys_mclk */ 743 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 744 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 745 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 746 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 747 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 748 >; 749 }; 750 751 pinctrl_cam_mclk: cammclkgrp { 752 fsl,pins = < 753 /* Parallel Camera CAM sys_mclk */ 754 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 755 >; 756 }; 757 758 /* CSI pins used as GPIOs */ 759 pinctrl_csi_gpio_1: csigpio1grp { 760 fsl,pins = < 761 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 762 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 763 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 764 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 765 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 766 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 767 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 768 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 769 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 770 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 771 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 772 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 773 >; 774 }; 775 776 pinctrl_csi_gpio_2: csigpio2grp { 777 fsl,pins = < 778 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 779 >; 780 }; 781 782 pinctrl_ecspi4: ecspi4grp { 783 fsl,pins = < 784 /* SPI CS */ 785 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 786 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 787 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 788 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 789 >; 790 }; 791 792 pinctrl_enet: enetgrp { 793 fsl,pins = < 794 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 795 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 796 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 797 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 798 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 799 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 800 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 801 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 802 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 803 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 804 >; 805 }; 806 807 pinctrl_flexcan1: flexcan1grp { 808 fsl,pins = < 809 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 810 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 811 >; 812 }; 813 814 pinctrl_flexcan2: flexcan2grp { 815 fsl,pins = < 816 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 817 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 818 >; 819 }; 820 821 pinctrl_gpio_1: gpio1grp { 822 fsl,pins = < 823 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 824 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 825 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 826 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 827 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 828 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 829 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 830 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 831 >; 832 }; 833 pinctrl_gpio_2: gpio2grp { 834 fsl,pins = < 835 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 836 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 837 >; 838 }; 839 840 pinctrl_gpio_bl_on: gpioblongrp { 841 fsl,pins = < 842 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 843 >; 844 }; 845 846 pinctrl_gpio_keys: gpiokeysgrp { 847 fsl,pins = < 848 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 849 >; 850 }; 851 852 pinctrl_hdmi_ddc: hdmiddcgrp { 853 fsl,pins = < 854 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 855 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 856 >; 857 }; 858 859 pinctrl_i2c2: i2c2grp { 860 fsl,pins = < 861 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 862 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 863 >; 864 }; 865 866 pinctrl_i2c2_gpio: i2c2gpiogrp { 867 fsl,pins = < 868 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 869 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 870 >; 871 }; 872 873 pinctrl_i2c3: i2c3grp { 874 fsl,pins = < 875 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 876 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 877 >; 878 }; 879 880 pinctrl_i2c3_gpio: i2c3gpiogrp { 881 fsl,pins = < 882 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 883 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 884 >; 885 }; 886 887 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 888 fsl,pins = < 889 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 890 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 891 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 892 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 893 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 894 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 895 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 896 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 897 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 898 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 899 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 900 /* Disable PWM pins on camera interface */ 901 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 902 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 903 >; 904 }; 905 906 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 907 fsl,pins = < 908 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 909 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 910 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 911 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 912 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 913 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 914 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 915 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 916 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 917 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 918 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 919 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 920 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 921 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 922 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 923 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 924 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 925 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 926 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 927 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 928 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 929 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 930 >; 931 }; 932 933 pinctrl_lvds_transceiver: lvdstxgrp { 934 fsl,pins = < 935 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ 936 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ 937 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ 938 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ 939 >; 940 }; 941 942 pinctrl_mic_gnd: micgndgrp { 943 fsl,pins = < 944 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 945 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 946 >; 947 }; 948 949 pinctrl_mmc_cd: mmccdgrp { 950 fsl,pins = < 951 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 952 >; 953 }; 954 955 pinctrl_mmc_cd_sleep: mmccdslpgrp { 956 fsl,pins = < 957 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 958 >; 959 }; 960 961 pinctrl_pwm1: pwm1grp { 962 fsl,pins = < 963 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 964 >; 965 }; 966 967 pinctrl_pwm2: pwm2grp { 968 fsl,pins = < 969 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 970 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 971 >; 972 }; 973 974 pinctrl_pwm3: pwm3grp { 975 fsl,pins = < 976 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 977 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 978 >; 979 }; 980 981 pinctrl_pwm4: pwm4grp { 982 fsl,pins = < 983 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 984 >; 985 }; 986 987 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 988 fsl,pins = < 989 /* USBH_EN */ 990 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 991 >; 992 }; 993 994 pinctrl_spdif: spdifgrp { 995 fsl,pins = < 996 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 997 >; 998 }; 999 1000 pinctrl_touch_int: gpiotouchintgrp { 1001 fsl,pins = < 1002 /* STMPE811 interrupt */ 1003 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 1004 >; 1005 }; 1006 1007 pinctrl_uart1_dce: uart1dcegrp { 1008 fsl,pins = < 1009 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1010 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1011 >; 1012 }; 1013 1014 /* DTE mode */ 1015 pinctrl_uart1_dte: uart1dtegrp { 1016 fsl,pins = < 1017 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1018 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1019 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1020 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1021 >; 1022 }; 1023 1024 /* Additional DTR, DSR, DCD */ 1025 pinctrl_uart1_ctrl: uart1ctrlgrp { 1026 fsl,pins = < 1027 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1028 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1029 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1030 >; 1031 }; 1032 1033 pinctrl_uart2_dte: uart2dtegrp { 1034 fsl,pins = < 1035 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1036 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1037 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1038 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1039 >; 1040 }; 1041 1042 pinctrl_uart3_dte: uart3dtegrp { 1043 fsl,pins = < 1044 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1045 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1046 >; 1047 }; 1048 1049 pinctrl_usbc_det: usbcdetgrp { 1050 fsl,pins = < 1051 /* USBC_DET */ 1052 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 1053 /* USBC_DET_OVERWRITE */ 1054 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 1055 /* USBC_DET_EN */ 1056 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 1057 >; 1058 }; 1059 1060 pinctrl_usbc_id_1: usbcid1grp { 1061 fsl,pins = < 1062 /* USBC_ID */ 1063 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 1064 >; 1065 }; 1066 1067 pinctrl_usbh_oc_1: usbhoc1grp { 1068 fsl,pins = < 1069 /* USBH_OC */ 1070 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 1071 >; 1072 }; 1073 1074 pinctrl_usdhc1: usdhc1grp { 1075 fsl,pins = < 1076 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1077 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1078 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1079 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1080 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1081 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1082 >; 1083 }; 1084 1085 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1086 fsl,pins = < 1087 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 1088 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 1089 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 1090 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 1091 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 1092 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 1093 >; 1094 }; 1095 1096 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1097 fsl,pins = < 1098 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 1099 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 1100 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 1101 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 1102 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 1103 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 1104 >; 1105 }; 1106 1107 /* avoid backfeeding with removed card power */ 1108 pinctrl_usdhc1_sleep: usdhc1sleepgrp { 1109 fsl,pins = < 1110 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 1111 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 1112 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 1113 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 1114 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 1115 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 1116 >; 1117 }; 1118 1119 pinctrl_usdhc3: usdhc3grp { 1120 fsl,pins = < 1121 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1122 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1123 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1124 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1125 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1126 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1127 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1128 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1129 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1130 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1131 /* eMMC reset */ 1132 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1133 >; 1134 }; 1135 1136 pinctrl_weim_cs0: weimcs0grp { 1137 fsl,pins = < 1138 /* nEXT_CS0 */ 1139 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1140 >; 1141 }; 1142 1143 pinctrl_weim_cs1: weimcs1grp { 1144 fsl,pins = < 1145 /* nEXT_CS1 */ 1146 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 1147 >; 1148 }; 1149 1150 pinctrl_weim_cs2: weimcs2grp { 1151 fsl,pins = < 1152 /* nEXT_CS2 */ 1153 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 1154 >; 1155 }; 1156 1157 /* ADDRESS[16:18] [25] used as GPIO */ 1158 pinctrl_weim_gpio_1: weimgpio1grp { 1159 fsl,pins = < 1160 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1161 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1162 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1163 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1164 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1165 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1166 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1167 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1168 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1169 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1170 >; 1171 }; 1172 1173 /* ADDRESS[19:24] used as GPIO */ 1174 pinctrl_weim_gpio_2: weimgpio2grp { 1175 fsl,pins = < 1176 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1177 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1178 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1179 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1180 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1181 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1182 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1183 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1184 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1185 >; 1186 }; 1187 1188 /* DATA[16:31] used as GPIO */ 1189 pinctrl_weim_gpio_3: weimgpio3grp { 1190 fsl,pins = < 1191 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 1192 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 1193 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 1194 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 1195 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 1196 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1197 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 1198 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 1199 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 1200 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 1201 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 1202 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 1203 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 1204 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 1205 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 1206 >; 1207 }; 1208 1209 /* DQM[0:3] used as GPIO */ 1210 pinctrl_weim_gpio_4: weimgpio4grp { 1211 fsl,pins = < 1212 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 1213 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 1214 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 1215 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 1216 >; 1217 }; 1218 1219 /* RDY used as GPIO */ 1220 pinctrl_weim_gpio_5: weimgpio5grp { 1221 fsl,pins = < 1222 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 1223 >; 1224 }; 1225 1226 /* ADDRESS[16] DATA[30] used as GPIO */ 1227 pinctrl_weim_gpio_6: weimgpio6grp { 1228 fsl,pins = < 1229 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 1230 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1231 >; 1232 }; 1233 1234 pinctrl_weim_npwe: weimnpwegrp { 1235 fsl,pins = < 1236 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 1237 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 1238 >; 1239 }; 1240 1241 pinctrl_weim_sram: weimsramgrp { 1242 fsl,pins = < 1243 /* Data */ 1244 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 1245 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 1246 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 1247 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 1248 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 1249 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 1250 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 1251 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 1252 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 1253 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 1254 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 1255 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 1256 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 1257 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 1258 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 1259 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 1260 /* Address */ 1261 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1262 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1263 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1264 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1265 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1266 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1267 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1268 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1269 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1270 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1271 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1272 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1273 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1274 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1275 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1276 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1277 /* Ctrl */ 1278 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1279 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1280 >; 1281 }; 1282 1283 pinctrl_weim_rdnwr: weimrdnwrgrp { 1284 fsl,pins = < 1285 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 1286 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 1287 >; 1288 }; 1289};