imx6qdl-skov-cpu.dtsi (10085B)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de> 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/leds/common.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 aliases { 14 can0 = &can1; 15 can1 = &can2; 16 mdio-gpio0 = &mdio; 17 nand = &gpmi; 18 rtc0 = &i2c_rtc; 19 rtc1 = &snvs; 20 usb0 = &usbh1; 21 usb1 = &usbotg; 22 }; 23 24 iio-hwmon { 25 compatible = "iio-hwmon"; 26 io-channels = <&adc 0>, /* 24V */ 27 <&adc 1>; /* temperature */ 28 }; 29 30 leds { 31 compatible = "gpio-leds"; 32 33 led-0 { 34 label = "D1"; 35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 36 function = LED_FUNCTION_STATUS; 37 default-state = "on"; 38 linux,default-trigger = "heartbeat"; 39 }; 40 41 led-1 { 42 label = "D2"; 43 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 44 default-state = "off"; 45 }; 46 47 led-2 { 48 label = "D3"; 49 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 50 default-state = "on"; 51 }; 52 }; 53 54 mdio: mdio { 55 compatible = "microchip,mdio-smi0"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_mdio>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, 61 <&gpio1 22 GPIO_ACTIVE_HIGH>; 62 63 switch@0 { 64 compatible = "microchip,ksz8873"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_switch>; 67 interrupt-parent = <&gpio3>; 68 interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; 69 reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 70 reg = <0>; 71 72 ports { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 ports@0 { 77 reg = <0>; 78 phy-mode = "internal"; 79 label = "lan1"; 80 }; 81 82 ports@1 { 83 reg = <1>; 84 phy-mode = "internal"; 85 label = "lan2"; 86 }; 87 88 ports@2 { 89 reg = <2>; 90 label = "cpu"; 91 ethernet = <&fec>; 92 phy-mode = "rmii"; 93 94 fixed-link { 95 speed = <100>; 96 full-duplex; 97 }; 98 }; 99 }; 100 }; 101 102 }; 103 104 clk50m_phy: phy-clock { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <50000000>; 108 }; 109 110 reg_3v3: regulator-3v3 { 111 compatible = "regulator-fixed"; 112 vin-supply = <®_5v0>; 113 regulator-name = "3v3"; 114 regulator-min-microvolt = <3300000>; 115 regulator-max-microvolt = <3300000>; 116 }; 117 118 reg_5v0: regulator-5v0 { 119 compatible = "regulator-fixed"; 120 regulator-name = "5v0"; 121 regulator-min-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>; 123 }; 124 125 reg_24v0: regulator-24v0 { 126 compatible = "regulator-fixed"; 127 regulator-name = "24v0"; 128 regulator-min-microvolt = <24000000>; 129 regulator-max-microvolt = <24000000>; 130 }; 131 132 reg_can1_stby: regulator-can1-stby { 133 compatible = "regulator-fixed"; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_can1_stby>; 136 regulator-name = "can1-3v3"; 137 regulator-min-microvolt = <3300000>; 138 regulator-max-microvolt = <3300000>; 139 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; 140 }; 141 142 reg_can2_stby: regulator-can2-stby { 143 compatible = "regulator-fixed"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_can2_stby>; 146 regulator-name = "can2-3v3"; 147 regulator-min-microvolt = <3300000>; 148 regulator-max-microvolt = <3300000>; 149 gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; 150 }; 151 152 reg_vcc_mmc: regulator-vcc-mmc { 153 compatible = "regulator-fixed"; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_vcc_mmc>; 156 vin-supply = <®_3v3>; 157 regulator-name = "mmc_vcc_supply"; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 regulator-always-on; 161 regulator-boot-on; 162 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 startup-delay-us = <100>; 165 }; 166 167 reg_vcc_mmc_io: regulator-vcc-mmc-io { 168 compatible = "regulator-gpio"; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_vcc_mmc_io>; 171 vin-supply = <®_5v0>; 172 regulator-name = "mmc_io_supply"; 173 regulator-type = "voltage"; 174 regulator-min-microvolt = <1800000>; 175 regulator-max-microvolt = <3300000>; 176 gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; 177 enable-active-high; 178 states = <1800000 0x1>, <3300000 0x0>; 179 startup-delay-us = <100>; 180 }; 181}; 182 183&can1 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_can1>; 186 xceiver-supply = <®_can1_stby>; 187 status = "okay"; 188}; 189 190&can2 { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_can2>; 193 xceiver-supply = <®_can2_stby>; 194 status = "okay"; 195}; 196 197&ecspi1 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_ecspi1>; 200 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 201 status = "okay"; 202 203 flash@0 { 204 compatible = "jedec,spi-nor"; 205 spi-max-frequency = <54000000>; 206 reg = <0>; 207 }; 208}; 209 210&ecspi2 { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_ecspi2>; 213 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 214 status = "okay"; 215 216 adc: adc@0 { 217 compatible = "microchip,mcp3002"; 218 reg = <0>; 219 vref-supply = <®_3v3>; 220 spi-max-frequency = <1000000>; 221 #io-channel-cells = <1>; 222 }; 223}; 224 225&fec { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_enet>; 228 clocks = <&clks IMX6QDL_CLK_ENET>, 229 <&clks IMX6QDL_CLK_ENET>, 230 <&clk50m_phy>; 231 clock-names = "ipg", "ahb", "ptp"; 232 phy-mode = "rmii"; 233 phy-supply = <®_3v3>; 234 status = "okay"; 235 236 fixed-link { 237 speed = <100>; 238 full-duplex; 239 }; 240}; 241 242&gpmi { 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_gpmi_nand>; 245 nand-on-flash-bbt; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 status = "okay"; 249}; 250 251&i2c3 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c3>; 254 clock-frequency = <400000>; 255 status = "okay"; 256 257 i2c_rtc: rtc@51 { 258 compatible = "nxp,pcf85063"; 259 reg = <0x51>; 260 quartz-load-femtofarads = <12500>; 261 }; 262}; 263 264&pwm2 { 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_pwm2>; 267 #pwm-cells = <2>; 268 status = "okay"; 269}; 270 271&pwm3 { 272 /* used for LCD contrast control */ 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_pwm3>; 275 status = "okay"; 276}; 277 278&uart2 { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_uart2>; 281 status = "okay"; 282}; 283 284&usbh1 { 285 vbus-supply = <®_5v0>; 286 disable-over-current; 287 status = "okay"; 288}; 289 290/* no usbh2 */ 291&usbphynop1 { 292 status = "disabled"; 293}; 294 295/* no usbh3 */ 296&usbphynop2 { 297 status = "disabled"; 298}; 299 300&usbotg { 301 vbus-supply = <®_5v0>; 302 disable-over-current; 303 status = "okay"; 304}; 305 306&usdhc3 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_usdhc3>; 309 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 310 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 311 cap-power-off-card; 312 full-pwr-cycle; 313 bus-width = <4>; 314 max-frequency = <50000000>; 315 cap-sd-highspeed; 316 sd-uhs-sdr12; 317 sd-uhs-sdr25; 318 sd-uhs-sdr50; 319 sd-uhs-ddr50; 320 mmc-ddr-1_8v; 321 vmmc-supply = <®_vcc_mmc>; 322 vqmmc-supply = <®_vcc_mmc_io>; 323 status = "okay"; 324}; 325 326&iomuxc { 327 pinctrl_can1: can1grp { 328 fsl,pins = < 329 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008 330 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000 331 >; 332 }; 333 334 pinctrl_can1_stby: can1stbygrp { 335 fsl,pins = < 336 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008 337 >; 338 }; 339 340 pinctrl_can2: can2grp { 341 fsl,pins = < 342 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 343 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 344 >; 345 }; 346 347 pinctrl_can2_stby: can2stbygrp { 348 fsl,pins = < 349 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008 350 >; 351 }; 352 353 pinctrl_ecspi1: ecspi1grp { 354 fsl,pins = < 355 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 356 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1 357 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1 358 /* *no* external pull up */ 359 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58 360 >; 361 }; 362 363 pinctrl_ecspi2: ecspi2grp { 364 fsl,pins = < 365 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 366 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1 367 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1 368 /* external pull up */ 369 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58 370 >; 371 }; 372 373 pinctrl_enet: enetgrp { 374 fsl,pins = < 375 /* RMII 50 MHz */ 376 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5 377 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5 378 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0 379 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0 380 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5 381 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5 382 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 383 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58 384 /* GPIO for "link active" */ 385 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038 386 >; 387 }; 388 389 pinctrl_gpmi_nand: gpminandgrp { 390 fsl,pins = < 391 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 392 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 393 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 394 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 395 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 396 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 397 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 398 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 399 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 400 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 401 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 402 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 403 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 404 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 405 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 406 >; 407 }; 408 409 pinctrl_i2c3: i2c3grp { 410 fsl,pins = < 411 /* external 10 k pull up */ 412 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878 413 /* external 10 k pull up */ 414 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878 415 >; 416 }; 417 418 pinctrl_mdio: mdiogrp { 419 fsl,pins = < 420 MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1 421 MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1 422 >; 423 }; 424 425 pinctrl_pwm2: pwm2grp { 426 fsl,pins = < 427 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58 428 >; 429 }; 430 431 pinctrl_pwm3: pwm3grp { 432 fsl,pins = < 433 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58 434 >; 435 }; 436 437 pinctrl_switch: switchgrp { 438 fsl,pins = < 439 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0 440 >; 441 }; 442 443 pinctrl_uart2: uart2grp { 444 fsl,pins = < 445 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 446 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 447 >; 448 }; 449 450 pinctrl_usdhc3: usdhc3grp { 451 fsl,pins = < 452 /* SoC internal pull up required */ 453 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 454 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 455 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 456 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 457 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 458 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 459 /* SoC internal pull up required */ 460 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040 461 /* SoC internal pull up required */ 462 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040 463 >; 464 }; 465 466 pinctrl_vcc_mmc: vccmmcgrp { 467 fsl,pins = < 468 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58 469 >; 470 }; 471 472 pinctrl_vcc_mmc_io: vccmmciogrp { 473 fsl,pins = < 474 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58 475 >; 476 }; 477};