cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6sl-evk.dts (16207B)


      1// SPDX-License-Identifier: GPL-2.0
      2//
      3//Copyright (C) 2013 Freescale Semiconductor, Inc.
      4
      5/dts-v1/;
      6
      7#include <dt-bindings/gpio/gpio.h>
      8#include <dt-bindings/input/input.h>
      9#include "imx6sl.dtsi"
     10
     11/ {
     12	model = "Freescale i.MX6 SoloLite EVK Board";
     13	compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
     14
     15	chosen {
     16		stdout-path = &uart1;
     17	};
     18
     19	memory@80000000 {
     20		device_type = "memory";
     21		reg = <0x80000000 0x40000000>;
     22	};
     23
     24	backlight_display: backlight_display {
     25		compatible = "pwm-backlight";
     26		pwms = <&pwm1 0 5000000>;
     27		brightness-levels = <0 4 8 16 32 64 128 255>;
     28		default-brightness-level = <6>;
     29	};
     30
     31	leds {
     32		compatible = "gpio-leds";
     33		pinctrl-names = "default";
     34		pinctrl-0 = <&pinctrl_led>;
     35
     36		user {
     37			label = "debug";
     38			gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
     39			linux,default-trigger = "heartbeat";
     40		};
     41	};
     42
     43	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
     44		compatible = "regulator-fixed";
     45		regulator-name = "usb_otg1_vbus";
     46		regulator-min-microvolt = <5000000>;
     47		regulator-max-microvolt = <5000000>;
     48		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
     49		enable-active-high;
     50		vin-supply = <&swbst_reg>;
     51	};
     52
     53	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
     54		compatible = "regulator-fixed";
     55		regulator-name = "usb_otg2_vbus";
     56		regulator-min-microvolt = <5000000>;
     57		regulator-max-microvolt = <5000000>;
     58		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
     59		enable-active-high;
     60		vin-supply = <&swbst_reg>;
     61	};
     62
     63	reg_aud3v: regulator-aud3v {
     64		compatible = "regulator-fixed";
     65		regulator-name = "wm8962-supply-3v15";
     66		regulator-min-microvolt = <3150000>;
     67		regulator-max-microvolt = <3150000>;
     68		regulator-boot-on;
     69	};
     70
     71	reg_aud4v: regulator-aud4v {
     72		compatible = "regulator-fixed";
     73		regulator-name = "wm8962-supply-4v2";
     74		regulator-min-microvolt = <4325000>;
     75		regulator-max-microvolt = <4325000>;
     76		regulator-boot-on;
     77	};
     78
     79	reg_lcd_3v3: regulator-lcd-3v3 {
     80		compatible = "regulator-fixed";
     81		pinctrl-names = "default";
     82		pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
     83		regulator-name = "lcd-3v3";
     84		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
     85		enable-active-high;
     86	};
     87
     88	reg_lcd_5v: regulator-lcd-5v {
     89		compatible = "regulator-fixed";
     90		regulator-name = "lcd-5v0";
     91		regulator-min-microvolt = <5000000>;
     92		regulator-max-microvolt = <5000000>;
     93	};
     94
     95	sound {
     96		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
     97		pinctrl-names = "default";
     98		pinctrl-0 = <&pinctrl_hp>;
     99		model = "wm8962-audio";
    100		ssi-controller = <&ssi2>;
    101		audio-codec = <&codec>;
    102		audio-routing =
    103			"Headphone Jack", "HPOUTL",
    104			"Headphone Jack", "HPOUTR",
    105			"Ext Spk", "SPKOUTL",
    106			"Ext Spk", "SPKOUTR",
    107			"AMIC", "MICBIAS",
    108			"IN3R", "AMIC";
    109		mux-int-port = <2>;
    110		mux-ext-port = <3>;
    111		hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
    112	};
    113
    114	panel {
    115		compatible = "sii,43wvf1g";
    116		backlight = <&backlight_display>;
    117		dvdd-supply = <&reg_lcd_3v3>;
    118		avdd-supply = <&reg_lcd_5v>;
    119
    120		port {
    121			panel_in: endpoint {
    122				remote-endpoint = <&display_out>;
    123			};
    124		};
    125	};
    126};
    127
    128&audmux {
    129	pinctrl-names = "default";
    130	pinctrl-0 = <&pinctrl_audmux3>;
    131	status = "okay";
    132};
    133
    134&ecspi1 {
    135	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
    136	pinctrl-names = "default";
    137	pinctrl-0 = <&pinctrl_ecspi1>;
    138	status = "okay";
    139
    140	flash: flash@0 {
    141		#address-cells = <1>;
    142		#size-cells = <1>;
    143		compatible = "st,m25p32", "jedec,spi-nor";
    144		spi-max-frequency = <20000000>;
    145		reg = <0>;
    146	};
    147};
    148
    149&fec {
    150	pinctrl-names = "default", "sleep";
    151	pinctrl-0 = <&pinctrl_fec>;
    152	pinctrl-1 = <&pinctrl_fec_sleep>;
    153	phy-mode = "rmii";
    154	status = "okay";
    155};
    156
    157&i2c1 {
    158	clock-frequency = <100000>;
    159	pinctrl-names = "default";
    160	pinctrl-0 = <&pinctrl_i2c1>;
    161	status = "okay";
    162
    163	pmic: pfuze100@8 {
    164		compatible = "fsl,pfuze100";
    165		reg = <0x08>;
    166
    167		regulators {
    168			sw1a_reg: sw1ab {
    169				regulator-min-microvolt = <300000>;
    170				regulator-max-microvolt = <1875000>;
    171				regulator-boot-on;
    172				regulator-always-on;
    173				regulator-ramp-delay = <6250>;
    174			};
    175
    176			sw1c_reg: sw1c {
    177				regulator-min-microvolt = <300000>;
    178				regulator-max-microvolt = <1875000>;
    179				regulator-boot-on;
    180				regulator-always-on;
    181				regulator-ramp-delay = <6250>;
    182			};
    183
    184			sw2_reg: sw2 {
    185				regulator-min-microvolt = <800000>;
    186				regulator-max-microvolt = <3300000>;
    187				regulator-boot-on;
    188				regulator-always-on;
    189			};
    190
    191			sw3a_reg: sw3a {
    192				regulator-min-microvolt = <400000>;
    193				regulator-max-microvolt = <1975000>;
    194				regulator-boot-on;
    195				regulator-always-on;
    196			};
    197
    198			sw3b_reg: sw3b {
    199				regulator-min-microvolt = <400000>;
    200				regulator-max-microvolt = <1975000>;
    201				regulator-boot-on;
    202				regulator-always-on;
    203			};
    204
    205			sw4_reg: sw4 {
    206				regulator-min-microvolt = <800000>;
    207				regulator-max-microvolt = <3300000>;
    208				regulator-always-on;
    209			};
    210
    211			swbst_reg: swbst {
    212				regulator-min-microvolt = <5000000>;
    213				regulator-max-microvolt = <5150000>;
    214			};
    215
    216			snvs_reg: vsnvs {
    217				regulator-min-microvolt = <1000000>;
    218				regulator-max-microvolt = <3000000>;
    219				regulator-boot-on;
    220				regulator-always-on;
    221			};
    222
    223			vref_reg: vrefddr {
    224				regulator-boot-on;
    225				regulator-always-on;
    226			};
    227
    228			vgen1_reg: vgen1 {
    229				regulator-min-microvolt = <800000>;
    230				regulator-max-microvolt = <1550000>;
    231				regulator-always-on;
    232			};
    233
    234			vgen2_reg: vgen2 {
    235				regulator-min-microvolt = <800000>;
    236				regulator-max-microvolt = <1550000>;
    237			};
    238
    239			vgen3_reg: vgen3 {
    240				regulator-min-microvolt = <1800000>;
    241				regulator-max-microvolt = <3300000>;
    242			};
    243
    244			vgen4_reg: vgen4 {
    245				regulator-min-microvolt = <1800000>;
    246				regulator-max-microvolt = <3300000>;
    247				regulator-always-on;
    248			};
    249
    250			vgen5_reg: vgen5 {
    251				regulator-min-microvolt = <1800000>;
    252				regulator-max-microvolt = <3300000>;
    253				regulator-always-on;
    254			};
    255
    256			vgen6_reg: vgen6 {
    257				regulator-min-microvolt = <1800000>;
    258				regulator-max-microvolt = <3300000>;
    259				regulator-always-on;
    260			};
    261		};
    262	};
    263};
    264
    265&i2c2 {
    266	clock-frequency = <100000>;
    267	pinctrl-names = "default";
    268	pinctrl-0 = <&pinctrl_i2c2>;
    269	status = "okay";
    270
    271	codec: wm8962@1a {
    272		compatible = "wlf,wm8962";
    273		reg = <0x1a>;
    274		clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
    275		DCVDD-supply = <&vgen3_reg>;
    276		DBVDD-supply = <&reg_aud3v>;
    277		AVDD-supply = <&vgen3_reg>;
    278		CPVDD-supply = <&vgen3_reg>;
    279		MICVDD-supply = <&reg_aud3v>;
    280		PLLVDD-supply = <&vgen3_reg>;
    281		SPKVDD1-supply = <&reg_aud4v>;
    282		SPKVDD2-supply = <&reg_aud4v>;
    283	};
    284};
    285
    286&iomuxc {
    287	pinctrl-names = "default";
    288	pinctrl-0 = <&pinctrl_hog>;
    289
    290	imx6sl-evk {
    291		pinctrl_hog: hoggrp {
    292			fsl,pins = <
    293				MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
    294				MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
    295				MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
    296				MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
    297				MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
    298				MX6SL_PAD_KEY_COL4__GPIO4_IO00	0x80000000
    299				MX6SL_PAD_KEY_COL5__GPIO4_IO02	0x80000000
    300				MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
    301			>;
    302		};
    303
    304		pinctrl_audmux3: audmux3grp {
    305			fsl,pins = <
    306				MX6SL_PAD_AUD_RXD__AUD3_RXD	  0x4130b0
    307				MX6SL_PAD_AUD_TXC__AUD3_TXC	  0x4130b0
    308				MX6SL_PAD_AUD_TXD__AUD3_TXD	  0x4110b0
    309				MX6SL_PAD_AUD_TXFS__AUD3_TXFS	  0x4130b0
    310			>;
    311		};
    312
    313		pinctrl_ecspi1: ecspi1grp {
    314			fsl,pins = <
    315				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
    316				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
    317				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
    318				MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11	0x80000000
    319			>;
    320		};
    321
    322		pinctrl_fec: fecgrp {
    323			fsl,pins = <
    324				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
    325				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
    326				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
    327				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
    328				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
    329				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
    330				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
    331				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
    332				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
    333			>;
    334		};
    335
    336		pinctrl_fec_sleep: fecgrp-sleep {
    337			fsl,pins = <
    338				MX6SL_PAD_FEC_MDC__GPIO4_IO23      0x3080
    339				MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25   0x3080
    340				MX6SL_PAD_FEC_RXD0__GPIO4_IO17     0x3080
    341				MX6SL_PAD_FEC_RXD1__GPIO4_IO18     0x3080
    342				MX6SL_PAD_FEC_TX_EN__GPIO4_IO22    0x3080
    343				MX6SL_PAD_FEC_TXD0__GPIO4_IO24     0x3080
    344				MX6SL_PAD_FEC_TXD1__GPIO4_IO16     0x3080
    345				MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26  0x3080
    346			>;
    347		};
    348
    349		pinctrl_hp: hpgrp {
    350			fsl,pins = <
    351				MX6SL_PAD_FEC_RX_ER__GPIO4_IO19	  0x1b0b0
    352			>;
    353		};
    354
    355		pinctrl_i2c1: i2c1grp {
    356			fsl,pins = <
    357				MX6SL_PAD_I2C1_SCL__I2C1_SCL	0x4001b8b1
    358				MX6SL_PAD_I2C1_SDA__I2C1_SDA	0x4001b8b1
    359			>;
    360		};
    361
    362
    363		pinctrl_i2c2: i2c2grp {
    364			fsl,pins = <
    365				MX6SL_PAD_I2C2_SCL__I2C2_SCL	0x4001b8b1
    366				MX6SL_PAD_I2C2_SDA__I2C2_SDA	0x4001b8b1
    367			>;
    368		};
    369
    370		pinctrl_kpp: kppgrp {
    371			fsl,pins = <
    372				MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
    373				MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
    374				MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
    375				MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
    376				MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
    377				MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
    378			>;
    379		};
    380
    381		pinctrl_lcd: lcdgrp {
    382			fsl,pins = <
    383				MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
    384				MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
    385				MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
    386				MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
    387				MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
    388				MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
    389				MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
    390				MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
    391				MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
    392				MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
    393				MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
    394				MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
    395				MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
    396				MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
    397				MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
    398				MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
    399				MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
    400				MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
    401				MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
    402				MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
    403				MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
    404				MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
    405				MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
    406				MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
    407				MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
    408				MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
    409				MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
    410				MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
    411			>;
    412		};
    413
    414		pinctrl_led: ledgrp {
    415			fsl,pins = <
    416				MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
    417			>;
    418		};
    419
    420		pinctrl_pwm1: pwmgrp {
    421			fsl,pins = <
    422				MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
    423			>;
    424		};
    425
    426		pinctrl_reg_lcd_3v3: reglcd3v3grp {
    427			fsl,pins = <
    428				MX6SL_PAD_KEY_ROW5__GPIO4_IO03    0x17059
    429			>;
    430		};
    431
    432		pinctrl_uart1: uart1grp {
    433			fsl,pins = <
    434				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x1b0b1
    435				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x1b0b1
    436			>;
    437		};
    438
    439		pinctrl_usbotg1: usbotg1grp {
    440			fsl,pins = <
    441				MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID	0x17059
    442			>;
    443		};
    444
    445		pinctrl_usdhc1: usdhc1grp {
    446			fsl,pins = <
    447				MX6SL_PAD_SD1_CMD__SD1_CMD		0x17059
    448				MX6SL_PAD_SD1_CLK__SD1_CLK		0x10059
    449				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x17059
    450				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x17059
    451				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x17059
    452				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x17059
    453				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x17059
    454				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x17059
    455				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x17059
    456				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x17059
    457			>;
    458		};
    459
    460		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
    461			fsl,pins = <
    462				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170b9
    463				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100b9
    464				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170b9
    465				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170b9
    466				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170b9
    467				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170b9
    468				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170b9
    469				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170b9
    470				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170b9
    471				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170b9
    472			>;
    473		};
    474
    475		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
    476			fsl,pins = <
    477				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170f9
    478				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100f9
    479				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
    480				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
    481				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
    482				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
    483				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170f9
    484				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170f9
    485				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170f9
    486				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170f9
    487			>;
    488		};
    489
    490		pinctrl_usdhc2: usdhc2grp {
    491			fsl,pins = <
    492				MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
    493				MX6SL_PAD_SD2_CLK__SD2_CLK		0x10059
    494				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
    495				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
    496				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
    497				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
    498			>;
    499		};
    500
    501		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
    502			fsl,pins = <
    503				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
    504				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100b9
    505				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
    506				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
    507				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
    508				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
    509			>;
    510		};
    511
    512		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
    513			fsl,pins = <
    514				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
    515				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100f9
    516				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
    517				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
    518				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
    519				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
    520			>;
    521		};
    522
    523		pinctrl_usdhc3: usdhc3grp {
    524			fsl,pins = <
    525				MX6SL_PAD_SD3_CMD__SD3_CMD		0x17059
    526				MX6SL_PAD_SD3_CLK__SD3_CLK		0x10059
    527				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x17059
    528				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x17059
    529				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x17059
    530				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x17059
    531			>;
    532		};
    533
    534		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
    535			fsl,pins = <
    536				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170b9
    537				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100b9
    538				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
    539				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
    540				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
    541				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
    542			>;
    543		};
    544
    545		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
    546			fsl,pins = <
    547				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170f9
    548				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100f9
    549				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
    550				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
    551				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
    552				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
    553			>;
    554		};
    555	};
    556};
    557
    558&kpp {
    559	pinctrl-names = "default";
    560	pinctrl-0 = <&pinctrl_kpp>;
    561	linux,keymap = <
    562			MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
    563			MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
    564			MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
    565			MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
    566			MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
    567			MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
    568			MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
    569			MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
    570	>;
    571	status = "okay";
    572};
    573
    574&lcdif {
    575	pinctrl-names = "default";
    576	pinctrl-0 = <&pinctrl_lcd>;
    577	status = "okay";
    578
    579	port {
    580		display_out: endpoint {
    581			remote-endpoint = <&panel_in>;
    582		};
    583	};
    584};
    585
    586&pwm1 {
    587	#pwm-cells = <2>;
    588	pinctrl-names = "default";
    589	pinctrl-0 = <&pinctrl_pwm1>;
    590	status = "okay";
    591};
    592
    593&reg_vdd1p1 {
    594	vin-supply = <&sw2_reg>;
    595};
    596
    597&reg_vdd2p5 {
    598	vin-supply = <&sw2_reg>;
    599};
    600
    601&snvs_poweroff {
    602	status = "okay";
    603};
    604
    605&ssi2 {
    606	status = "okay";
    607};
    608
    609&uart1 {
    610	pinctrl-names = "default";
    611	pinctrl-0 = <&pinctrl_uart1>;
    612	status = "okay";
    613};
    614
    615&usbotg1 {
    616	vbus-supply = <&reg_usb_otg1_vbus>;
    617	pinctrl-names = "default";
    618	pinctrl-0 = <&pinctrl_usbotg1>;
    619	disable-over-current;
    620	status = "okay";
    621};
    622
    623&usbotg2 {
    624	vbus-supply = <&reg_usb_otg2_vbus>;
    625	dr_mode = "host";
    626	disable-over-current;
    627	status = "okay";
    628};
    629
    630&usdhc1 {
    631	pinctrl-names = "default", "state_100mhz", "state_200mhz";
    632	pinctrl-0 = <&pinctrl_usdhc1>;
    633	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
    634	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
    635	bus-width = <8>;
    636	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
    637	wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
    638	status = "okay";
    639};
    640
    641&usdhc2 {
    642	pinctrl-names = "default", "state_100mhz", "state_200mhz";
    643	pinctrl-0 = <&pinctrl_usdhc2>;
    644	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
    645	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
    646	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
    647	wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
    648	status = "okay";
    649};
    650
    651&usdhc3 {
    652	pinctrl-names = "default", "state_100mhz", "state_200mhz";
    653	pinctrl-0 = <&pinctrl_usdhc3>;
    654	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
    655	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
    656	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
    657	status = "okay";
    658};