cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

imx6ul-liteboard.dts (4281B)

      1/*
      2 * Copyright 2016 Grinn
      3 *
      4 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
      5 *
      6 * This file is dual-licensed: you can use it either under the terms
      7 * of the GPL or the X11 license, at your option. Note that this dual
      8 * licensing only applies to this file, and not this project as a
      9 * whole.
     10 *
     11 *  a) This file is free software; you can redistribute it and/or
     12 *     modify it under the terms of the GNU General Public License
     13 *     version 2 as published by the Free Software Foundation.
     14 *
     15 *     This file is distributed in the hope that it will be useful,
     16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     18 *     GNU General Public License for more details.
     19 *
     20 * Or, alternatively,
     21 *
     22 *  b) Permission is hereby granted, free of charge, to any person
     23 *     obtaining a copy of this software and associated documentation
     24 *     files (the "Software"), to deal in the Software without
     25 *     restriction, including without limitation the rights to use,
     26 *     copy, modify, merge, publish, distribute, sublicense, and/or
     27 *     sell copies of the Software, and to permit persons to whom the
     28 *     Software is furnished to do so, subject to the following
     29 *     conditions:
     30 *
     31 *     The above copyright notice and this permission notice shall be
     32 *     included in all copies or substantial portions of the Software.
     33 *
     34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     41 *     OTHER DEALINGS IN THE SOFTWARE.
     42 */
     43
     44/dts-v1/;
     45
     46#include "imx6ul-litesom.dtsi"
     47
     48/ {
     49	model = "Grinn i.MX6UL liteBoard";
     50	compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
     51		     "fsl,imx6ul";
     52
     53	chosen {
     54		stdout-path = &uart1;
     55	};
     56
     57	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
     58		compatible = "regulator-fixed";
     59		pinctrl-names = "default";
     60		pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
     61		regulator-name = "usb_otg1_vbus";
     62		regulator-min-microvolt = <5000000>;
     63		regulator-max-microvolt = <5000000>;
     64		gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
     65	};
     66};
     67
     68&iomuxc {
     69	pinctrl_enet1: enet1grp {
     70		fsl,pins = <
     71			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
     72			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
     73			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
     74			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
     75			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
     76			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
     77			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
     78			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
     79			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
     80			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
     81		>;
     82	};
     83
     84	pinctrl_uart1: uart1grp {
     85		fsl,pins = <
     86			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
     87			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
     88		>;
     89	};
     90
     91	pinctrl_usdhc1: usdhc1grp {
     92		fsl,pins = <
     93			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
     94			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
     95			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
     96			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
     97			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
     98			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
     99			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
    100		>;
    101	};
    102
    103	pinctrl_usb_otg1_vbus: usb-otg1-vbus {
    104		fsl,pins = <
    105			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x79
    106		>;
    107	};
    108};
    109
    110&fec1 {
    111	pinctrl-names = "default";
    112	pinctrl-0 = <&pinctrl_enet1>;
    113	phy-mode = "rmii";
    114	phy-handle = <&ethphy0>;
    115	status = "okay";
    116
    117	mdio {
    118		#address-cells = <1>;
    119		#size-cells = <0>;
    120
    121		ethphy0: ethernet-phy@0 {
    122			reg = <0>;
    123		};
    124	};
    125};
    126
    127&snvs_poweroff {
    128	status = "okay";
    129};
    130
    131&uart1 {
    132	pinctrl-names = "default";
    133	pinctrl-0 = <&pinctrl_uart1>;
    134	status = "okay";
    135};
    136
    137&usbotg1 {
    138	vbus-supply = <&reg_usb_otg1_vbus>;
    139	dr_mode = "host";
    140	status = "okay";
    141};
    142
    143&usdhc1 {
    144	pinctrl-names = "default";
    145	pinctrl-0 = <&pinctrl_usdhc1>;
    146	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
    147	no-1-8-v;
    148	keep-power-in-suspend;
    149	wakeup-source;
    150	status = "okay";
    151};