cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6ul-tqma6ul1-mba6ulx.dts (1039B)

      1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
      2/*
      3 * Copyright 2018-2022 TQ-Systems GmbH
      4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
      5 */
      6
      7/dts-v1/;
      8
      9#include "imx6ul-tqma6ul1.dtsi"
     10#include "mba6ulx.dtsi"
     11
     12/ {
     13	model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
     14	compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
     15};
     16
     17/*
     18 * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
     19 * and need to be disabled here again
     20 */
     21&can2 {
     22	status = "disabled";
     23};
     24
     25&fec1 {
     26	pinctrl-names = "default";
     27	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
     28	status = "okay";
     29
     30	mdio {
     31		#address-cells = <1>;
     32		#size-cells = <0>;
     33
     34		ethphy0: ethernet-phy@0 {
     35			compatible = "ethernet-phy-ieee802.3-c22";
     36			max-speed = <100>;
     37			reg = <0>;
     38		};
     39	};
     40};
     41
     42&fec2 {
     43	/delete-property/ phy-handle;
     44	/delete-node/ mdio;
     45};
     46
     47&iomuxc {
     48	pinctrl_enet1_mdc: enet1mdcgrp {
     49		fsl,pins = <
     50			/* mdio */
     51			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
     52			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
     53		>;
     54	};
     55};