cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6ul.dtsi (32000B)


      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright 2015 Freescale Semiconductor, Inc.
      4
      5#include <dt-bindings/clock/imx6ul-clock.h>
      6#include <dt-bindings/gpio/gpio.h>
      7#include <dt-bindings/input/input.h>
      8#include <dt-bindings/interrupt-controller/arm-gic.h>
      9#include "imx6ul-pinfunc.h"
     10
     11/ {
     12	#address-cells = <1>;
     13	#size-cells = <1>;
     14	/*
     15	 * The decompressor and also some bootloaders rely on a
     16	 * pre-existing /chosen node to be available to insert the
     17	 * command line and merge other ATAGS info.
     18	 */
     19	chosen {};
     20
     21	aliases {
     22		ethernet0 = &fec1;
     23		ethernet1 = &fec2;
     24		gpio0 = &gpio1;
     25		gpio1 = &gpio2;
     26		gpio2 = &gpio3;
     27		gpio3 = &gpio4;
     28		gpio4 = &gpio5;
     29		i2c0 = &i2c1;
     30		i2c1 = &i2c2;
     31		i2c2 = &i2c3;
     32		i2c3 = &i2c4;
     33		mmc0 = &usdhc1;
     34		mmc1 = &usdhc2;
     35		serial0 = &uart1;
     36		serial1 = &uart2;
     37		serial2 = &uart3;
     38		serial3 = &uart4;
     39		serial4 = &uart5;
     40		serial5 = &uart6;
     41		serial6 = &uart7;
     42		serial7 = &uart8;
     43		sai1 = &sai1;
     44		sai2 = &sai2;
     45		sai3 = &sai3;
     46		spi0 = &ecspi1;
     47		spi1 = &ecspi2;
     48		spi2 = &ecspi3;
     49		spi3 = &ecspi4;
     50		usb0 = &usbotg1;
     51		usb1 = &usbotg2;
     52		usbphy0 = &usbphy1;
     53		usbphy1 = &usbphy2;
     54	};
     55
     56	cpus {
     57		#address-cells = <1>;
     58		#size-cells = <0>;
     59
     60		cpu0: cpu@0 {
     61			compatible = "arm,cortex-a7";
     62			device_type = "cpu";
     63			reg = <0>;
     64			clock-frequency = <696000000>;
     65			clock-latency = <61036>; /* two CLK32 periods */
     66			#cooling-cells = <2>;
     67			operating-points = <
     68				/* kHz	uV */
     69				696000	1275000
     70				528000	1175000
     71				396000	1025000
     72				198000	950000
     73			>;
     74			fsl,soc-operating-points = <
     75				/* KHz	uV */
     76				696000	1275000
     77				528000	1175000
     78				396000	1175000
     79				198000	1175000
     80			>;
     81			clocks = <&clks IMX6UL_CLK_ARM>,
     82				 <&clks IMX6UL_CLK_PLL2_BUS>,
     83				 <&clks IMX6UL_CLK_PLL2_PFD2>,
     84				 <&clks IMX6UL_CA7_SECONDARY_SEL>,
     85				 <&clks IMX6UL_CLK_STEP>,
     86				 <&clks IMX6UL_CLK_PLL1_SW>,
     87				 <&clks IMX6UL_CLK_PLL1_SYS>;
     88			clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
     89				      "secondary_sel", "step", "pll1_sw",
     90				      "pll1_sys";
     91			arm-supply = <&reg_arm>;
     92			soc-supply = <&reg_soc>;
     93			nvmem-cells = <&cpu_speed_grade>;
     94			nvmem-cell-names = "speed_grade";
     95		};
     96	};
     97
     98	timer {
     99		compatible = "arm,armv7-timer";
    100		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
    101			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
    102			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
    103			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
    104		interrupt-parent = <&intc>;
    105		status = "disabled";
    106	};
    107
    108	ckil: clock-cli {
    109		compatible = "fixed-clock";
    110		#clock-cells = <0>;
    111		clock-frequency = <32768>;
    112		clock-output-names = "ckil";
    113	};
    114
    115	osc: clock-osc {
    116		compatible = "fixed-clock";
    117		#clock-cells = <0>;
    118		clock-frequency = <24000000>;
    119		clock-output-names = "osc";
    120	};
    121
    122	ipp_di0: clock-di0 {
    123		compatible = "fixed-clock";
    124		#clock-cells = <0>;
    125		clock-frequency = <0>;
    126		clock-output-names = "ipp_di0";
    127	};
    128
    129	ipp_di1: clock-di1 {
    130		compatible = "fixed-clock";
    131		#clock-cells = <0>;
    132		clock-frequency = <0>;
    133		clock-output-names = "ipp_di1";
    134	};
    135
    136	pmu {
    137		compatible = "arm,cortex-a7-pmu";
    138		interrupt-parent = <&gpc>;
    139		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
    140	};
    141
    142	soc {
    143		#address-cells = <1>;
    144		#size-cells = <1>;
    145		compatible = "simple-bus";
    146		interrupt-parent = <&gpc>;
    147		ranges;
    148
    149		ocram: sram@900000 {
    150			compatible = "mmio-sram";
    151			reg = <0x00900000 0x20000>;
    152		};
    153
    154		intc: interrupt-controller@a01000 {
    155			compatible = "arm,gic-400", "arm,cortex-a7-gic";
    156			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
    157			#interrupt-cells = <3>;
    158			interrupt-controller;
    159			interrupt-parent = <&intc>;
    160			reg = <0x00a01000 0x1000>,
    161			      <0x00a02000 0x2000>,
    162			      <0x00a04000 0x2000>,
    163			      <0x00a06000 0x2000>;
    164		};
    165
    166		dma_apbh: dma-apbh@1804000 {
    167			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
    168			reg = <0x01804000 0x2000>;
    169			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
    170				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
    171				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
    172				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
    173			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
    174			#dma-cells = <1>;
    175			dma-channels = <4>;
    176			clocks = <&clks IMX6UL_CLK_APBHDMA>;
    177		};
    178
    179		gpmi: nand-controller@1806000 {
    180			compatible = "fsl,imx6q-gpmi-nand";
    181			#address-cells = <1>;
    182			#size-cells = <1>;
    183			reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
    184			reg-names = "gpmi-nand", "bch";
    185			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
    186			interrupt-names = "bch";
    187			clocks = <&clks IMX6UL_CLK_GPMI_IO>,
    188				 <&clks IMX6UL_CLK_GPMI_APB>,
    189				 <&clks IMX6UL_CLK_GPMI_BCH>,
    190				 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
    191				 <&clks IMX6UL_CLK_PER_BCH>;
    192			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
    193				      "gpmi_bch_apb", "per1_bch";
    194			dmas = <&dma_apbh 0>;
    195			dma-names = "rx-tx";
    196			status = "disabled";
    197		};
    198
    199		aips1: bus@2000000 {
    200			compatible = "fsl,aips-bus", "simple-bus";
    201			#address-cells = <1>;
    202			#size-cells = <1>;
    203			reg = <0x02000000 0x100000>;
    204			ranges;
    205
    206			spba-bus@2000000 {
    207				compatible = "fsl,spba-bus", "simple-bus";
    208				#address-cells = <1>;
    209				#size-cells = <1>;
    210				reg = <0x02000000 0x40000>;
    211				ranges;
    212
    213				ecspi1: spi@2008000 {
    214					#address-cells = <1>;
    215					#size-cells = <0>;
    216					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
    217					reg = <0x02008000 0x4000>;
    218					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
    219					clocks = <&clks IMX6UL_CLK_ECSPI1>,
    220						 <&clks IMX6UL_CLK_ECSPI1>;
    221					clock-names = "ipg", "per";
    222					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
    223					dma-names = "rx", "tx";
    224					status = "disabled";
    225				};
    226
    227				ecspi2: spi@200c000 {
    228					#address-cells = <1>;
    229					#size-cells = <0>;
    230					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
    231					reg = <0x0200c000 0x4000>;
    232					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    233					clocks = <&clks IMX6UL_CLK_ECSPI2>,
    234						 <&clks IMX6UL_CLK_ECSPI2>;
    235					clock-names = "ipg", "per";
    236					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
    237					dma-names = "rx", "tx";
    238					status = "disabled";
    239				};
    240
    241				ecspi3: spi@2010000 {
    242					#address-cells = <1>;
    243					#size-cells = <0>;
    244					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
    245					reg = <0x02010000 0x4000>;
    246					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
    247					clocks = <&clks IMX6UL_CLK_ECSPI3>,
    248						 <&clks IMX6UL_CLK_ECSPI3>;
    249					clock-names = "ipg", "per";
    250					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
    251					dma-names = "rx", "tx";
    252					status = "disabled";
    253				};
    254
    255				ecspi4: spi@2014000 {
    256					#address-cells = <1>;
    257					#size-cells = <0>;
    258					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
    259					reg = <0x02014000 0x4000>;
    260					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
    261					clocks = <&clks IMX6UL_CLK_ECSPI4>,
    262						 <&clks IMX6UL_CLK_ECSPI4>;
    263					clock-names = "ipg", "per";
    264					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
    265					dma-names = "rx", "tx";
    266					status = "disabled";
    267				};
    268
    269				uart7: serial@2018000 {
    270					compatible = "fsl,imx6ul-uart",
    271						     "fsl,imx6q-uart";
    272					reg = <0x02018000 0x4000>;
    273					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    274					clocks = <&clks IMX6UL_CLK_UART7_IPG>,
    275						 <&clks IMX6UL_CLK_UART7_SERIAL>;
    276					clock-names = "ipg", "per";
    277					status = "disabled";
    278				};
    279
    280				uart1: serial@2020000 {
    281					compatible = "fsl,imx6ul-uart",
    282						     "fsl,imx6q-uart";
    283					reg = <0x02020000 0x4000>;
    284					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
    285					clocks = <&clks IMX6UL_CLK_UART1_IPG>,
    286						 <&clks IMX6UL_CLK_UART1_SERIAL>;
    287					clock-names = "ipg", "per";
    288					status = "disabled";
    289				};
    290
    291				uart8: serial@2024000 {
    292					compatible = "fsl,imx6ul-uart",
    293						     "fsl,imx6q-uart";
    294					reg = <0x02024000 0x4000>;
    295					interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    296					clocks = <&clks IMX6UL_CLK_UART8_IPG>,
    297						 <&clks IMX6UL_CLK_UART8_SERIAL>;
    298					clock-names = "ipg", "per";
    299					status = "disabled";
    300				};
    301
    302				sai1: sai@2028000 {
    303					#sound-dai-cells = <0>;
    304					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
    305					reg = <0x02028000 0x4000>;
    306					interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
    307					clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
    308						 <&clks IMX6UL_CLK_SAI1>,
    309						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
    310					clock-names = "bus", "mclk1", "mclk2", "mclk3";
    311					dmas = <&sdma 35 24 0>,
    312					       <&sdma 36 24 0>;
    313					dma-names = "rx", "tx";
    314					status = "disabled";
    315				};
    316
    317				sai2: sai@202c000 {
    318					#sound-dai-cells = <0>;
    319					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
    320					reg = <0x0202c000 0x4000>;
    321					interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
    322					clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
    323						 <&clks IMX6UL_CLK_SAI2>,
    324						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
    325					clock-names = "bus", "mclk1", "mclk2", "mclk3";
    326					dmas = <&sdma 37 24 0>,
    327					       <&sdma 38 24 0>;
    328					dma-names = "rx", "tx";
    329					status = "disabled";
    330				};
    331
    332				sai3: sai@2030000 {
    333					#sound-dai-cells = <0>;
    334					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
    335					reg = <0x02030000 0x4000>;
    336					interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
    337					clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
    338						 <&clks IMX6UL_CLK_SAI3>,
    339						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
    340					clock-names = "bus", "mclk1", "mclk2", "mclk3";
    341					dmas = <&sdma 39 24 0>,
    342					       <&sdma 40 24 0>;
    343					dma-names = "rx", "tx";
    344					status = "disabled";
    345				};
    346
    347				asrc: asrc@2034000 {
    348					compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
    349					reg = <0x2034000 0x4000>;
    350					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
    351					clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
    352						<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
    353						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
    354						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
    355						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
    356						<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
    357						<&clks IMX6UL_CLK_SPBA>;
    358					clock-names = "mem", "ipg", "asrck_0",
    359						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
    360						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
    361						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
    362						"asrck_d", "asrck_e", "asrck_f", "spba";
    363					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
    364						<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
    365					dma-names = "rxa", "rxb", "rxc",
    366						    "txa", "txb", "txc";
    367					fsl,asrc-rate  = <48000>;
    368					fsl,asrc-width = <16>;
    369					status = "okay";
    370				};
    371			};
    372
    373			tsc: tsc@2040000 {
    374				compatible = "fsl,imx6ul-tsc";
    375				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
    376				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
    377					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
    378				clocks = <&clks IMX6UL_CLK_IPG>,
    379					 <&clks IMX6UL_CLK_ADC2>;
    380				clock-names = "tsc", "adc";
    381				status = "disabled";
    382			};
    383
    384			pwm1: pwm@2080000 {
    385				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    386				reg = <0x02080000 0x4000>;
    387				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
    388				clocks = <&clks IMX6UL_CLK_PWM1>,
    389					 <&clks IMX6UL_CLK_PWM1>;
    390				clock-names = "ipg", "per";
    391				#pwm-cells = <3>;
    392				status = "disabled";
    393			};
    394
    395			pwm2: pwm@2084000 {
    396				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    397				reg = <0x02084000 0x4000>;
    398				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
    399				clocks = <&clks IMX6UL_CLK_PWM2>,
    400					 <&clks IMX6UL_CLK_PWM2>;
    401				clock-names = "ipg", "per";
    402				#pwm-cells = <3>;
    403				status = "disabled";
    404			};
    405
    406			pwm3: pwm@2088000 {
    407				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    408				reg = <0x02088000 0x4000>;
    409				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
    410				clocks = <&clks IMX6UL_CLK_PWM3>,
    411					 <&clks IMX6UL_CLK_PWM3>;
    412				clock-names = "ipg", "per";
    413				#pwm-cells = <3>;
    414				status = "disabled";
    415			};
    416
    417			pwm4: pwm@208c000 {
    418				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    419				reg = <0x0208c000 0x4000>;
    420				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
    421				clocks = <&clks IMX6UL_CLK_PWM4>,
    422					 <&clks IMX6UL_CLK_PWM4>;
    423				clock-names = "ipg", "per";
    424				#pwm-cells = <3>;
    425				status = "disabled";
    426			};
    427
    428			can1: can@2090000 {
    429				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
    430				reg = <0x02090000 0x4000>;
    431				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
    432				clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
    433					 <&clks IMX6UL_CLK_CAN1_SERIAL>;
    434				clock-names = "ipg", "per";
    435				fsl,stop-mode = <&gpr 0x10 1>;
    436				status = "disabled";
    437			};
    438
    439			can2: can@2094000 {
    440				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
    441				reg = <0x02094000 0x4000>;
    442				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
    443				clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
    444					 <&clks IMX6UL_CLK_CAN2_SERIAL>;
    445				clock-names = "ipg", "per";
    446				fsl,stop-mode = <&gpr 0x10 2>;
    447				status = "disabled";
    448			};
    449
    450			gpt1: timer@2098000 {
    451				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
    452				reg = <0x02098000 0x4000>;
    453				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
    454				clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
    455					 <&clks IMX6UL_CLK_GPT1_SERIAL>;
    456				clock-names = "ipg", "per";
    457			};
    458
    459			gpio1: gpio@209c000 {
    460				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    461				reg = <0x0209c000 0x4000>;
    462				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
    463					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
    464				clocks = <&clks IMX6UL_CLK_GPIO1>;
    465				gpio-controller;
    466				#gpio-cells = <2>;
    467				interrupt-controller;
    468				#interrupt-cells = <2>;
    469				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
    470					      <&iomuxc 16 33 16>;
    471			};
    472
    473			gpio2: gpio@20a0000 {
    474				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    475				reg = <0x020a0000 0x4000>;
    476				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
    477					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
    478				clocks = <&clks IMX6UL_CLK_GPIO2>;
    479				gpio-controller;
    480				#gpio-cells = <2>;
    481				interrupt-controller;
    482				#interrupt-cells = <2>;
    483				gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
    484			};
    485
    486			gpio3: gpio@20a4000 {
    487				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    488				reg = <0x020a4000 0x4000>;
    489				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
    490					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
    491				clocks = <&clks IMX6UL_CLK_GPIO3>;
    492				gpio-controller;
    493				#gpio-cells = <2>;
    494				interrupt-controller;
    495				#interrupt-cells = <2>;
    496				gpio-ranges = <&iomuxc 0 65 29>;
    497			};
    498
    499			gpio4: gpio@20a8000 {
    500				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    501				reg = <0x020a8000 0x4000>;
    502				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
    503					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
    504				clocks = <&clks IMX6UL_CLK_GPIO4>;
    505				gpio-controller;
    506				#gpio-cells = <2>;
    507				interrupt-controller;
    508				#interrupt-cells = <2>;
    509				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
    510			};
    511
    512			gpio5: gpio@20ac000 {
    513				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
    514				reg = <0x020ac000 0x4000>;
    515				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
    516					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
    517				clocks = <&clks IMX6UL_CLK_GPIO5>;
    518				gpio-controller;
    519				#gpio-cells = <2>;
    520				interrupt-controller;
    521				#interrupt-cells = <2>;
    522				gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
    523			};
    524
    525			fec2: ethernet@20b4000 {
    526				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
    527				reg = <0x020b4000 0x4000>;
    528				interrupt-names = "int0", "pps";
    529				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
    530					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    531				clocks = <&clks IMX6UL_CLK_ENET>,
    532					 <&clks IMX6UL_CLK_ENET_AHB>,
    533					 <&clks IMX6UL_CLK_ENET_PTP>,
    534					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
    535					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
    536				clock-names = "ipg", "ahb", "ptp",
    537					      "enet_clk_ref", "enet_out";
    538				fsl,num-tx-queues = <1>;
    539				fsl,num-rx-queues = <1>;
    540				fsl,stop-mode = <&gpr 0x10 4>;
    541				fsl,magic-packet;
    542				status = "disabled";
    543			};
    544
    545			kpp: keypad@20b8000 {
    546				compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
    547				reg = <0x020b8000 0x4000>;
    548				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
    549				clocks = <&clks IMX6UL_CLK_KPP>;
    550				status = "disabled";
    551			};
    552
    553			wdog1: watchdog@20bc000 {
    554				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
    555				reg = <0x020bc000 0x4000>;
    556				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
    557				clocks = <&clks IMX6UL_CLK_WDOG1>;
    558			};
    559
    560			wdog2: watchdog@20c0000 {
    561				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
    562				reg = <0x020c0000 0x4000>;
    563				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
    564				clocks = <&clks IMX6UL_CLK_WDOG2>;
    565				status = "disabled";
    566			};
    567
    568			clks: clock-controller@20c4000 {
    569				compatible = "fsl,imx6ul-ccm";
    570				reg = <0x020c4000 0x4000>;
    571				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
    572					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
    573				#clock-cells = <1>;
    574				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
    575				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
    576			};
    577
    578			anatop: anatop@20c8000 {
    579				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
    580					     "syscon", "simple-mfd";
    581				reg = <0x020c8000 0x1000>;
    582				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
    583					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
    584					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
    585
    586				reg_3p0: regulator-3p0 {
    587					compatible = "fsl,anatop-regulator";
    588					regulator-name = "vdd3p0";
    589					regulator-min-microvolt = <2625000>;
    590					regulator-max-microvolt = <3400000>;
    591					anatop-reg-offset = <0x120>;
    592					anatop-vol-bit-shift = <8>;
    593					anatop-vol-bit-width = <5>;
    594					anatop-min-bit-val = <0>;
    595					anatop-min-voltage = <2625000>;
    596					anatop-max-voltage = <3400000>;
    597					anatop-enable-bit = <0>;
    598				};
    599
    600				reg_arm: regulator-vddcore {
    601					compatible = "fsl,anatop-regulator";
    602					regulator-name = "cpu";
    603					regulator-min-microvolt = <725000>;
    604					regulator-max-microvolt = <1450000>;
    605					regulator-always-on;
    606					anatop-reg-offset = <0x140>;
    607					anatop-vol-bit-shift = <0>;
    608					anatop-vol-bit-width = <5>;
    609					anatop-delay-reg-offset = <0x170>;
    610					anatop-delay-bit-shift = <24>;
    611					anatop-delay-bit-width = <2>;
    612					anatop-min-bit-val = <1>;
    613					anatop-min-voltage = <725000>;
    614					anatop-max-voltage = <1450000>;
    615				};
    616
    617				reg_soc: regulator-vddsoc {
    618					compatible = "fsl,anatop-regulator";
    619					regulator-name = "vddsoc";
    620					regulator-min-microvolt = <725000>;
    621					regulator-max-microvolt = <1450000>;
    622					regulator-always-on;
    623					anatop-reg-offset = <0x140>;
    624					anatop-vol-bit-shift = <18>;
    625					anatop-vol-bit-width = <5>;
    626					anatop-delay-reg-offset = <0x170>;
    627					anatop-delay-bit-shift = <28>;
    628					anatop-delay-bit-width = <2>;
    629					anatop-min-bit-val = <1>;
    630					anatop-min-voltage = <725000>;
    631					anatop-max-voltage = <1450000>;
    632				};
    633
    634				tempmon: tempmon {
    635					compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
    636					interrupt-parent = <&gpc>;
    637					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
    638					fsl,tempmon = <&anatop>;
    639					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
    640					nvmem-cell-names = "calib", "temp_grade";
    641					clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
    642				};
    643			};
    644
    645			usbphy1: usbphy@20c9000 {
    646				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
    647				reg = <0x020c9000 0x1000>;
    648				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
    649				clocks = <&clks IMX6UL_CLK_USBPHY1>;
    650				phy-3p0-supply = <&reg_3p0>;
    651				fsl,anatop = <&anatop>;
    652			};
    653
    654			usbphy2: usbphy@20ca000 {
    655				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
    656				reg = <0x020ca000 0x1000>;
    657				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    658				clocks = <&clks IMX6UL_CLK_USBPHY2>;
    659				phy-3p0-supply = <&reg_3p0>;
    660				fsl,anatop = <&anatop>;
    661			};
    662
    663			snvs: snvs@20cc000 {
    664				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
    665				reg = <0x020cc000 0x4000>;
    666
    667				snvs_rtc: snvs-rtc-lp {
    668					compatible = "fsl,sec-v4.0-mon-rtc-lp";
    669					regmap = <&snvs>;
    670					offset = <0x34>;
    671					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
    672						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
    673				};
    674
    675				snvs_poweroff: snvs-poweroff {
    676					compatible = "syscon-poweroff";
    677					regmap = <&snvs>;
    678					offset = <0x38>;
    679					value = <0x60>;
    680					mask = <0x60>;
    681					status = "disabled";
    682				};
    683
    684				snvs_pwrkey: snvs-powerkey {
    685					compatible = "fsl,sec-v4.0-pwrkey";
    686					regmap = <&snvs>;
    687					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
    688					linux,keycode = <KEY_POWER>;
    689					wakeup-source;
    690					status = "disabled";
    691				};
    692
    693				snvs_lpgpr: snvs-lpgpr {
    694					compatible = "fsl,imx6ul-snvs-lpgpr";
    695				};
    696			};
    697
    698			epit1: epit@20d0000 {
    699				reg = <0x020d0000 0x4000>;
    700				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
    701			};
    702
    703			epit2: epit@20d4000 {
    704				reg = <0x020d4000 0x4000>;
    705				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    706			};
    707
    708			src: reset-controller@20d8000 {
    709				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
    710				reg = <0x020d8000 0x4000>;
    711				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
    712					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
    713				#reset-cells = <1>;
    714			};
    715
    716			gpc: gpc@20dc000 {
    717				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
    718				reg = <0x020dc000 0x4000>;
    719				interrupt-controller;
    720				#interrupt-cells = <3>;
    721				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
    722				interrupt-parent = <&intc>;
    723			};
    724
    725			iomuxc: pinctrl@20e0000 {
    726				compatible = "fsl,imx6ul-iomuxc";
    727				reg = <0x020e0000 0x4000>;
    728			};
    729
    730			gpr: iomuxc-gpr@20e4000 {
    731				compatible = "fsl,imx6ul-iomuxc-gpr",
    732					     "fsl,imx6q-iomuxc-gpr", "syscon";
    733				reg = <0x020e4000 0x4000>;
    734			};
    735
    736			gpt2: timer@20e8000 {
    737				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
    738				reg = <0x020e8000 0x4000>;
    739				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
    740				clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
    741					 <&clks IMX6UL_CLK_GPT2_SERIAL>;
    742				clock-names = "ipg", "per";
    743				status = "disabled";
    744			};
    745
    746			sdma: sdma@20ec000 {
    747				compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
    748					     "fsl,imx35-sdma";
    749				reg = <0x020ec000 0x4000>;
    750				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
    751				clocks = <&clks IMX6UL_CLK_IPG>,
    752					 <&clks IMX6UL_CLK_SDMA>;
    753				clock-names = "ipg", "ahb";
    754				#dma-cells = <3>;
    755				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
    756			};
    757
    758			pwm5: pwm@20f0000 {
    759				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    760				reg = <0x020f0000 0x4000>;
    761				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
    762				clocks = <&clks IMX6UL_CLK_PWM5>,
    763					 <&clks IMX6UL_CLK_PWM5>;
    764				clock-names = "ipg", "per";
    765				#pwm-cells = <3>;
    766				status = "disabled";
    767			};
    768
    769			pwm6: pwm@20f4000 {
    770				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    771				reg = <0x020f4000 0x4000>;
    772				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
    773				clocks = <&clks IMX6UL_CLK_PWM6>,
    774					 <&clks IMX6UL_CLK_PWM6>;
    775				clock-names = "ipg", "per";
    776				#pwm-cells = <3>;
    777				status = "disabled";
    778			};
    779
    780			pwm7: pwm@20f8000 {
    781				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    782				reg = <0x020f8000 0x4000>;
    783				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
    784				clocks = <&clks IMX6UL_CLK_PWM7>,
    785					 <&clks IMX6UL_CLK_PWM7>;
    786				clock-names = "ipg", "per";
    787				#pwm-cells = <3>;
    788				status = "disabled";
    789			};
    790
    791			pwm8: pwm@20fc000 {
    792				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
    793				reg = <0x020fc000 0x4000>;
    794				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
    795				clocks = <&clks IMX6UL_CLK_PWM8>,
    796					 <&clks IMX6UL_CLK_PWM8>;
    797				clock-names = "ipg", "per";
    798				#pwm-cells = <3>;
    799				status = "disabled";
    800			};
    801		};
    802
    803		aips2: bus@2100000 {
    804			compatible = "fsl,aips-bus", "simple-bus";
    805			#address-cells = <1>;
    806			#size-cells = <1>;
    807			reg = <0x02100000 0x100000>;
    808			ranges;
    809
    810			crypto: crypto@2140000 {
    811				compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
    812				#address-cells = <1>;
    813				#size-cells = <1>;
    814				reg = <0x2140000 0x3c000>;
    815				ranges = <0 0x2140000 0x3c000>;
    816				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    817				clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
    818					 <&clks IMX6UL_CLK_CAAM_MEM>;
    819				clock-names = "ipg", "aclk", "mem";
    820
    821				sec_jr0: jr@1000 {
    822					compatible = "fsl,sec-v4.0-job-ring";
    823					reg = <0x1000 0x1000>;
    824					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
    825				};
    826
    827				sec_jr1: jr@2000 {
    828					compatible = "fsl,sec-v4.0-job-ring";
    829					reg = <0x2000 0x1000>;
    830					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
    831				};
    832
    833				sec_jr2: jr@3000 {
    834					compatible = "fsl,sec-v4.0-job-ring";
    835					reg = <0x3000 0x1000>;
    836					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    837				};
    838			};
    839
    840			usbotg1: usb@2184000 {
    841				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
    842				reg = <0x02184000 0x200>;
    843				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
    844				clocks = <&clks IMX6UL_CLK_USBOH3>;
    845				fsl,usbphy = <&usbphy1>;
    846				fsl,usbmisc = <&usbmisc 0>;
    847				fsl,anatop = <&anatop>;
    848				ahb-burst-config = <0x0>;
    849				tx-burst-size-dword = <0x10>;
    850				rx-burst-size-dword = <0x10>;
    851				status = "disabled";
    852			};
    853
    854			usbotg2: usb@2184200 {
    855				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
    856				reg = <0x02184200 0x200>;
    857				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
    858				clocks = <&clks IMX6UL_CLK_USBOH3>;
    859				fsl,usbphy = <&usbphy2>;
    860				fsl,usbmisc = <&usbmisc 1>;
    861				ahb-burst-config = <0x0>;
    862				tx-burst-size-dword = <0x10>;
    863				rx-burst-size-dword = <0x10>;
    864				status = "disabled";
    865			};
    866
    867			usbmisc: usbmisc@2184800 {
    868				#index-cells = <1>;
    869				compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
    870				reg = <0x02184800 0x200>;
    871			};
    872
    873			fec1: ethernet@2188000 {
    874				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
    875				reg = <0x02188000 0x4000>;
    876				interrupt-names = "int0", "pps";
    877				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
    878					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
    879				clocks = <&clks IMX6UL_CLK_ENET>,
    880					 <&clks IMX6UL_CLK_ENET_AHB>,
    881					 <&clks IMX6UL_CLK_ENET_PTP>,
    882					 <&clks IMX6UL_CLK_ENET_REF>,
    883					 <&clks IMX6UL_CLK_ENET_REF>;
    884				clock-names = "ipg", "ahb", "ptp",
    885					      "enet_clk_ref", "enet_out";
    886				fsl,num-tx-queues = <1>;
    887				fsl,num-rx-queues = <1>;
    888				fsl,stop-mode = <&gpr 0x10 3>;
    889				fsl,magic-packet;
    890				status = "disabled";
    891			};
    892
    893			usdhc1: mmc@2190000 {
    894				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
    895				reg = <0x02190000 0x4000>;
    896				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
    897				clocks = <&clks IMX6UL_CLK_USDHC1>,
    898					 <&clks IMX6UL_CLK_USDHC1>,
    899					 <&clks IMX6UL_CLK_USDHC1>;
    900				clock-names = "ipg", "ahb", "per";
    901				fsl,tuning-step = <2>;
    902				fsl,tuning-start-tap = <20>;
    903				bus-width = <4>;
    904				status = "disabled";
    905			};
    906
    907			usdhc2: mmc@2194000 {
    908				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
    909				reg = <0x02194000 0x4000>;
    910				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
    911				clocks = <&clks IMX6UL_CLK_USDHC2>,
    912					 <&clks IMX6UL_CLK_USDHC2>,
    913					 <&clks IMX6UL_CLK_USDHC2>;
    914				clock-names = "ipg", "ahb", "per";
    915				bus-width = <4>;
    916				fsl,tuning-step = <2>;
    917				fsl,tuning-start-tap = <20>;
    918				status = "disabled";
    919			};
    920
    921			adc1: adc@2198000 {
    922				compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
    923				reg = <0x02198000 0x4000>;
    924				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
    925				clocks = <&clks IMX6UL_CLK_ADC1>;
    926				num-channels = <2>;
    927				clock-names = "adc";
    928				fsl,adck-max-frequency = <30000000>, <40000000>,
    929							 <20000000>;
    930				status = "disabled";
    931			};
    932
    933			i2c1: i2c@21a0000 {
    934				#address-cells = <1>;
    935				#size-cells = <0>;
    936				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
    937				reg = <0x021a0000 0x4000>;
    938				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
    939				clocks = <&clks IMX6UL_CLK_I2C1>;
    940				status = "disabled";
    941			};
    942
    943			i2c2: i2c@21a4000 {
    944				#address-cells = <1>;
    945				#size-cells = <0>;
    946				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
    947				reg = <0x021a4000 0x4000>;
    948				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
    949				clocks = <&clks IMX6UL_CLK_I2C2>;
    950				status = "disabled";
    951			};
    952
    953			i2c3: i2c@21a8000 {
    954				#address-cells = <1>;
    955				#size-cells = <0>;
    956				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
    957				reg = <0x021a8000 0x4000>;
    958				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    959				clocks = <&clks IMX6UL_CLK_I2C3>;
    960				status = "disabled";
    961			};
    962
    963			memory-controller@21b0000 {
    964				compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
    965				reg = <0x021b0000 0x4000>;
    966				clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
    967			};
    968
    969			weim: weim@21b8000 {
    970				#address-cells = <2>;
    971				#size-cells = <1>;
    972				compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
    973				reg = <0x021b8000 0x4000>;
    974				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    975				clocks = <&clks IMX6UL_CLK_EIM>;
    976				fsl,weim-cs-gpr = <&gpr>;
    977				status = "disabled";
    978			};
    979
    980			ocotp: efuse@21bc000 {
    981				#address-cells = <1>;
    982				#size-cells = <1>;
    983				compatible = "fsl,imx6ul-ocotp", "syscon";
    984				reg = <0x021bc000 0x4000>;
    985				clocks = <&clks IMX6UL_CLK_OCOTP>;
    986
    987				tempmon_calib: calib@38 {
    988					reg = <0x38 4>;
    989				};
    990
    991				tempmon_temp_grade: temp-grade@20 {
    992					reg = <0x20 4>;
    993				};
    994
    995				cpu_speed_grade: speed-grade@10 {
    996					reg = <0x10 4>;
    997				};
    998			};
    999
   1000			csi: csi@21c4000 {
   1001				compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
   1002				reg = <0x021c4000 0x4000>;
   1003				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
   1004				clocks = <&clks IMX6UL_CLK_CSI>;
   1005				clock-names = "mclk";
   1006				status = "disabled";
   1007			};
   1008
   1009			lcdif: lcdif@21c8000 {
   1010				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
   1011				reg = <0x021c8000 0x4000>;
   1012				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
   1013				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
   1014					 <&clks IMX6UL_CLK_LCDIF_APB>,
   1015					 <&clks IMX6UL_CLK_DUMMY>;
   1016				clock-names = "pix", "axi", "disp_axi";
   1017				status = "disabled";
   1018			};
   1019
   1020			pxp: pxp@21cc000 {
   1021				compatible = "fsl,imx6ul-pxp";
   1022				reg = <0x021cc000 0x4000>;
   1023				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
   1024				clocks = <&clks IMX6UL_CLK_PXP>;
   1025				clock-names = "axi";
   1026			};
   1027
   1028			qspi: spi@21e0000 {
   1029				#address-cells = <1>;
   1030				#size-cells = <0>;
   1031				compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
   1032				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
   1033				reg-names = "QuadSPI", "QuadSPI-memory";
   1034				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
   1035				clocks = <&clks IMX6UL_CLK_QSPI>,
   1036					 <&clks IMX6UL_CLK_QSPI>;
   1037				clock-names = "qspi_en", "qspi";
   1038				status = "disabled";
   1039			};
   1040
   1041			wdog3: watchdog@21e4000 {
   1042				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
   1043				reg = <0x021e4000 0x4000>;
   1044				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
   1045				clocks = <&clks IMX6UL_CLK_WDOG3>;
   1046				status = "disabled";
   1047			};
   1048
   1049			uart2: serial@21e8000 {
   1050				compatible = "fsl,imx6ul-uart",
   1051					     "fsl,imx6q-uart";
   1052				reg = <0x021e8000 0x4000>;
   1053				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
   1054				clocks = <&clks IMX6UL_CLK_UART2_IPG>,
   1055					 <&clks IMX6UL_CLK_UART2_SERIAL>;
   1056				clock-names = "ipg", "per";
   1057				status = "disabled";
   1058			};
   1059
   1060			uart3: serial@21ec000 {
   1061				compatible = "fsl,imx6ul-uart",
   1062					     "fsl,imx6q-uart";
   1063				reg = <0x021ec000 0x4000>;
   1064				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
   1065				clocks = <&clks IMX6UL_CLK_UART3_IPG>,
   1066					 <&clks IMX6UL_CLK_UART3_SERIAL>;
   1067				clock-names = "ipg", "per";
   1068				status = "disabled";
   1069			};
   1070
   1071			uart4: serial@21f0000 {
   1072				compatible = "fsl,imx6ul-uart",
   1073					     "fsl,imx6q-uart";
   1074				reg = <0x021f0000 0x4000>;
   1075				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
   1076				clocks = <&clks IMX6UL_CLK_UART4_IPG>,
   1077					 <&clks IMX6UL_CLK_UART4_SERIAL>;
   1078				clock-names = "ipg", "per";
   1079				status = "disabled";
   1080			};
   1081
   1082			uart5: serial@21f4000 {
   1083				compatible = "fsl,imx6ul-uart",
   1084					     "fsl,imx6q-uart";
   1085				reg = <0x021f4000 0x4000>;
   1086				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
   1087				clocks = <&clks IMX6UL_CLK_UART5_IPG>,
   1088					 <&clks IMX6UL_CLK_UART5_SERIAL>;
   1089				clock-names = "ipg", "per";
   1090				status = "disabled";
   1091			};
   1092
   1093			i2c4: i2c@21f8000 {
   1094				#address-cells = <1>;
   1095				#size-cells = <0>;
   1096				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
   1097				reg = <0x021f8000 0x4000>;
   1098				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
   1099				clocks = <&clks IMX6UL_CLK_I2C4>;
   1100				status = "disabled";
   1101			};
   1102
   1103			uart6: serial@21fc000 {
   1104				compatible = "fsl,imx6ul-uart",
   1105					     "fsl,imx6q-uart";
   1106				reg = <0x021fc000 0x4000>;
   1107				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
   1108				clocks = <&clks IMX6UL_CLK_UART6_IPG>,
   1109					 <&clks IMX6UL_CLK_UART6_SERIAL>;
   1110				clock-names = "ipg", "per";
   1111				status = "disabled";
   1112			};
   1113		};
   1114	};
   1115};