imx6ull-colibri.dtsi (19945B)
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2018-2022 Toradex 4 */ 5 6#include "imx6ull.dtsi" 7 8/ { 9 /* Ethernet aliases to ensure correct MAC addresses */ 10 aliases { 11 ethernet0 = &fec2; 12 ethernet1 = &fec1; 13 }; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 4 8 16 32 64 128 255>; 18 default-brightness-level = <6>; 19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_3v3>; 23 pwms = <&pwm4 0 5000000 1>; 24 status = "okay"; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_snvs_gpiokeys>; 31 32 wakeup { 33 debounce-interval = <10>; 34 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ 35 label = "Wake-Up"; 36 linux,code = <KEY_WAKEUP>; 37 wakeup-source; 38 }; 39 }; 40 41 panel_dpi: panel-dpi { 42 compatible = "edt,et057090dhu"; 43 backlight = <&backlight>; 44 power-supply = <®_3v3>; 45 status = "okay"; 46 47 port { 48 lcd_panel_in: endpoint { 49 remote-endpoint = <&lcdif_out>; 50 }; 51 }; 52 }; 53 54 reg_module_3v3: regulator-module-3v3 { 55 compatible = "regulator-fixed"; 56 regulator-always-on; 57 regulator-name = "+V3.3"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 }; 61 62 reg_module_3v3_avdd: regulator-module-3v3-avdd { 63 compatible = "regulator-fixed"; 64 regulator-always-on; 65 regulator-name = "+V3.3_AVDD_AUDIO"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 }; 69 70 reg_sd1_vqmmc: regulator-sd1-vqmmc { 71 compatible = "regulator-gpio"; 72 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 75 regulator-always-on; 76 regulator-name = "+V3.3_1.8_SD"; 77 regulator-min-microvolt = <1800000>; 78 regulator-max-microvolt = <3300000>; 79 states = <1800000 0x1 3300000 0x0>; 80 vin-supply = <®_module_3v3>; 81 }; 82 83 reg_eth_phy: regulator-eth-phy { 84 compatible = "regulator-fixed-clock"; 85 regulator-boot-on; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 regulator-name = "+V3.3_ETH"; 89 regulator-type = "voltage"; 90 vin-supply = <®_module_3v3>; 91 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 92 startup-delay-us = <150000>; 93 }; 94}; 95 96&adc1 { 97 num-channels = <10>; 98 vref-supply = <®_module_3v3_avdd>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_adc1>; 101}; 102 103&can1 { 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_flexcan1>; 106 status = "disabled"; 107}; 108 109&can2 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_flexcan2>; 112 status = "disabled"; 113}; 114 115/* Colibri SPI */ 116&ecspi1 { 117 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 120}; 121 122/* Ethernet */ 123&fec2 { 124 pinctrl-names = "default", "sleep"; 125 pinctrl-0 = <&pinctrl_enet2>; 126 pinctrl-1 = <&pinctrl_enet2_sleep>; 127 phy-mode = "rmii"; 128 phy-handle = <ðphy1>; 129 phy-supply = <®_eth_phy>; 130 status = "okay"; 131 132 mdio { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 ethphy1: ethernet-phy@2 { 137 compatible = "ethernet-phy-ieee802.3-c22"; 138 max-speed = <100>; 139 reg = <2>; 140 }; 141 }; 142}; 143 144/* NAND */ 145&gpmi { 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_gpmi_nand>; 148 fsl,use-minimum-ecc; 149 nand-on-flash-bbt; 150 nand-ecc-mode = "hw"; 151 nand-ecc-strength = <8>; 152 nand-ecc-step-size = <512>; 153 status = "okay"; 154}; 155 156/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ 157&i2c1 { 158 pinctrl-names = "default", "gpio"; 159 pinctrl-0 = <&pinctrl_i2c1>; 160 pinctrl-1 = <&pinctrl_i2c1_gpio>; 161 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 162 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 163 status = "okay"; 164 165 /* Atmel maxtouch controller */ 166 atmel_mxt_ts: touchscreen@4a { 167 compatible = "atmel,maxtouch"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_atmel_conn>; 170 reg = <0x4a>; 171 interrupt-parent = <&gpio5>; 172 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ 173 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ 174 status = "disabled"; 175 }; 176}; 177 178/* 179 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 180 * touch screen controller 181 */ 182&i2c2 { 183 /* Use low frequency to compensate for the high pull-up values. */ 184 clock-frequency = <40000>; 185 pinctrl-names = "default", "gpio"; 186 pinctrl-0 = <&pinctrl_i2c2>; 187 pinctrl-1 = <&pinctrl_i2c2_gpio>; 188 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 189 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 190 status = "okay"; 191 192 ad7879_ts: touchscreen@2c { 193 compatible = "adi,ad7879-1"; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 196 reg = <0x2c>; 197 interrupt-parent = <&gpio5>; 198 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 199 touchscreen-max-pressure = <4096>; 200 adi,resistance-plate-x = <120>; 201 adi,first-conversion-delay = /bits/ 8 <3>; 202 adi,acquisition-time = /bits/ 8 <1>; 203 adi,median-filter-size = /bits/ 8 <2>; 204 adi,averaging = /bits/ 8 <1>; 205 adi,conversion-interval = /bits/ 8 <255>; 206 }; 207}; 208 209&lcdif { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_lcdif_dat 212 &pinctrl_lcdif_ctrl>; 213 214 port { 215 lcdif_out: endpoint { 216 remote-endpoint = <&lcd_panel_in>; 217 }; 218 }; 219}; 220 221/* PWM <A> */ 222&pwm4 { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_pwm4>; 225}; 226 227/* PWM <B> */ 228&pwm5 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_pwm5>; 231}; 232 233/* PWM <C> */ 234&pwm6 { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_pwm6>; 237}; 238 239/* PWM <D> */ 240&pwm7 { 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_pwm7>; 243}; 244 245&sdma { 246 status = "okay"; 247}; 248 249&snvs_pwrkey { 250 status = "disabled"; 251}; 252 253/* Colibri UART_A */ 254&uart1 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 257 uart-has-rtscts; 258 fsl,dte-mode; 259}; 260 261/* Colibri UART_B */ 262&uart2 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_uart2>; 265 uart-has-rtscts; 266 fsl,dte-mode; 267}; 268 269/* Colibri UART_C */ 270&uart5 { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_uart5>; 273 fsl,dte-mode; 274}; 275 276/* Colibri USBC */ 277&usbotg1 { 278 dr_mode = "otg"; 279 srp-disable; 280 hnp-disable; 281 adp-disable; 282}; 283 284/* Colibri USBH */ 285&usbotg2 { 286 dr_mode = "host"; 287}; 288 289/* Colibri MMC/SD */ 290&usdhc1 { 291 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 292 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 293 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 294 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 295 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; 296 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 297 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 298 assigned-clock-rates = <0>, <198000000>; 299 bus-width = <4>; 300 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 301 disable-wp; 302 keep-power-in-suspend; 303 no-1-8-v; 304 vqmmc-supply = <®_sd1_vqmmc>; 305 wakeup-source; 306}; 307 308&wdog1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_wdog>; 311 fsl,ext-reset-output; 312}; 313 314&iomuxc { 315 pinctrl_adc1: adc1grp { 316 fsl,pins = < 317 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ 318 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ 319 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ 320 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ 321 >; 322 }; 323 324 pinctrl_atmel_adap: atmeladapgrp { 325 fsl,pins = < 326 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ 327 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ 328 >; 329 }; 330 331 pinctrl_atmel_conn: atmelconngrp { 332 fsl,pins = < 333 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ 334 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ 335 >; 336 }; 337 338 pinctrl_can_int: canintgrp { 339 fsl,pins = < 340 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ 341 >; 342 }; 343 344 pinctrl_enet2: enet2grp { 345 fsl,pins = < 346 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 347 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 348 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 349 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 350 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 351 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 352 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 353 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 354 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 355 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 356 >; 357 }; 358 359 pinctrl_enet2_sleep: enet2-sleepgrp { 360 fsl,pins = < 361 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 362 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 363 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 364 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 365 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 366 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 367 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 368 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 369 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 370 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 371 >; 372 }; 373 374 pinctrl_ecspi1_cs: ecspi1csgrp { 375 fsl,pins = < 376 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ 377 >; 378 }; 379 380 pinctrl_ecspi1: ecspi1grp { 381 fsl,pins = < 382 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ 383 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ 384 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ 385 >; 386 }; 387 388 pinctrl_flexcan1: flexcan1grp { 389 fsl,pins = < 390 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 391 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 392 >; 393 }; 394 395 pinctrl_flexcan2: flexcan2grp { 396 fsl,pins = < 397 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 398 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 399 >; 400 }; 401 402 pinctrl_gpio_bl_on: gpioblongrp { 403 fsl,pins = < 404 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ 405 >; 406 }; 407 408 pinctrl_gpio1: gpio1grp { 409 fsl,pins = < 410 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ 411 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ 412 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ 413 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ 414 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ 415 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ 416 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ 417 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ 418 >; 419 }; 420 421 pinctrl_gpio2: gpio2grp { /* Camera */ 422 fsl,pins = < 423 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ 424 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ 425 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ 426 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ 427 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ 428 >; 429 }; 430 431 pinctrl_gpio3: gpio3grp { /* CAN2 */ 432 fsl,pins = < 433 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ 434 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ 435 >; 436 }; 437 438 pinctrl_gpio4: gpio4grp { 439 fsl,pins = < 440 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ 441 >; 442 }; 443 444 pinctrl_gpio6: gpio6grp { /* Wifi pins */ 445 fsl,pins = < 446 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ 447 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ 448 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ 449 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ 450 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ 451 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ 452 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ 453 >; 454 }; 455 456 pinctrl_gpio7: gpio7grp { /* CAN1 */ 457 fsl,pins = < 458 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ 459 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ 460 >; 461 }; 462 463 /* 464 * With an eMMC instead of a raw NAND device the following pins 465 * are available at SODIMM pins. 466 */ 467 pinctrl_gpmi_gpio: gpmigpiogrp { 468 fsl,pins = < 469 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ 470 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ 471 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ 472 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ 473 >; 474 }; 475 476 pinctrl_gpmi_nand: gpminandgrp { 477 fsl,pins = < 478 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 479 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 480 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 481 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 482 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 483 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 484 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 485 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 486 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 487 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 488 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 489 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 490 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 491 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 492 >; 493 }; 494 495 pinctrl_i2c1: i2c1grp { 496 fsl,pins = < 497 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ 498 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ 499 >; 500 }; 501 502 pinctrl_i2c1_gpio: i2c1-gpiogrp { 503 fsl,pins = < 504 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ 505 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ 506 >; 507 }; 508 509 pinctrl_i2c2: i2c2grp { 510 fsl,pins = < 511 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 512 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 513 >; 514 }; 515 516 pinctrl_i2c2_gpio: i2c2-gpiogrp { 517 fsl,pins = < 518 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 519 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 520 >; 521 }; 522 523 pinctrl_lcdif_dat: lcdifdatgrp { 524 fsl,pins = < 525 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ 526 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ 527 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ 528 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ 529 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ 530 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ 531 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ 532 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ 533 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ 534 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ 535 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ 536 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ 537 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ 538 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ 539 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ 540 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ 541 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ 542 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ 543 >; 544 }; 545 546 pinctrl_lcdif_ctrl: lcdifctrlgrp { 547 fsl,pins = < 548 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ 549 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ 550 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ 551 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ 552 >; 553 }; 554 555 pinctrl_pwm4: pwm4grp { 556 fsl,pins = < 557 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ 558 >; 559 }; 560 561 pinctrl_pwm5: pwm5grp { 562 fsl,pins = < 563 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ 564 >; 565 }; 566 567 pinctrl_pwm6: pwm6grp { 568 fsl,pins = < 569 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ 570 >; 571 }; 572 573 pinctrl_pwm7: pwm7grp { 574 fsl,pins = < 575 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ 576 >; 577 }; 578 579 pinctrl_uart1: uart1grp { 580 fsl,pins = < 581 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ 582 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ 583 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ 584 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ 585 >; 586 }; 587 588 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ 589 fsl,pins = < 590 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ 591 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ 592 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ 593 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ 594 >; 595 }; 596 597 pinctrl_uart2: uart2grp { 598 fsl,pins = < 599 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ 600 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ 601 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ 602 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ 603 >; 604 }; 605 pinctrl_uart5: uart5grp { 606 fsl,pins = < 607 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ 608 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ 609 >; 610 }; 611 612 pinctrl_usbh_reg: usbhreggrp { 613 fsl,pins = < 614 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ 615 >; 616 }; 617 618 pinctrl_usdhc1: usdhc1grp { 619 fsl,pins = < 620 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ 621 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ 622 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ 623 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ 624 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ 625 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ 626 >; 627 }; 628 629 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 630 fsl,pins = < 631 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 632 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 633 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 634 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 635 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 636 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 637 >; 638 }; 639 640 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 641 fsl,pins = < 642 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 643 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 644 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 645 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 646 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 647 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 648 >; 649 }; 650 651 pinctrl_usdhc2: usdhc2grp { 652 fsl,pins = < 653 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 654 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 655 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 656 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 657 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 658 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 659 660 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 661 >; 662 }; 663 664 pinctrl_usdhc2emmc: usdhc2emmcgrp { 665 fsl,pins = < 666 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 667 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 668 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 669 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 670 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 671 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 672 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 673 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 674 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 675 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 676 >; 677 }; 678 679 pinctrl_wdog: wdoggrp { 680 fsl,pins = < 681 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 682 >; 683 }; 684}; 685 686&iomuxc_snvs { 687 pinctrl_snvs_gpio1: snvsgpio1grp { 688 fsl,pins = < 689 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ 690 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ 691 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ 692 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ 693 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ 694 >; 695 }; 696 697 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ 698 fsl,pins = < 699 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ 700 >; 701 }; 702 703 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ 704 fsl,pins = < 705 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 706 >; 707 }; 708 709 pinctrl_snvs_reg_sd: snvsregsdgrp { 710 fsl,pins = < 711 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 712 >; 713 }; 714 715 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 716 fsl,pins = < 717 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 718 >; 719 }; 720 721 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { 722 fsl,pins = < 723 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ 724 >; 725 }; 726 727 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { 728 fsl,pins = < 729 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ 730 >; 731 }; 732 733 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { 734 fsl,pins = < 735 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 736 >; 737 }; 738 739 pinctrl_snvs_wifi_pdn: snvswifipdngrp { 740 fsl,pins = < 741 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 742 >; 743 }; 744};