cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx6ulz-bsh-smm-m2.dts (3580B)


      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Copyright (C) 2021 BSH Hausgeraete GmbH
      4 */
      5
      6/dts-v1/;
      7
      8#include <dt-bindings/input/input.h>
      9#include "imx6ulz.dtsi"
     10
     11/ {
     12	model = "BSH SMM M2";
     13	compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
     14
     15	chosen {
     16		stdout-path = &uart4;
     17	};
     18
     19	usdhc2_pwrseq: usdhc2-pwrseq {
     20		compatible = "mmc-pwrseq-simple";
     21		reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
     22	};
     23};
     24
     25&gpmi {
     26	pinctrl-names = "default";
     27	pinctrl-0 = <&pinctrl_gpmi_nand>;
     28	nand-on-flash-bbt;
     29	status = "okay";
     30};
     31
     32&uart3 {
     33	pinctrl-names = "default";
     34	pinctrl-0 = <&pinctrl_uart3>;
     35	uart-has-rtscts;
     36	status = "okay";
     37
     38	bluetooth {
     39		compatible = "brcm,bcm4330-bt";
     40		max-speed = <3000000>;
     41		shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
     42		device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
     43		host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
     44	};
     45};
     46
     47&uart4 {
     48	pinctrl-names = "default";
     49	pinctrl-0 = <&pinctrl_uart4>;
     50	status = "okay";
     51};
     52
     53&usbotg1 {
     54	dr_mode = "peripheral";
     55	srp-disable;
     56	hnp-disable;
     57	adp-disable;
     58	status = "okay";
     59};
     60
     61&usbphy1 {
     62	fsl,tx-d-cal = <106>;
     63};
     64
     65&usdhc2 {
     66	#address-cells = <1>;
     67	#size-cells = <0>;
     68	pinctrl-names = "default";
     69	pinctrl-0 = <&pinctrl_wlan>;
     70	bus-width = <4>;
     71	no-1-8-v;
     72	non-removable;
     73	cap-power-off-card;
     74	keep-power-in-suspend;
     75	cap-sdio-irq;
     76	mmc-pwrseq = <&usdhc2_pwrseq>;
     77	status = "okay";
     78
     79	brcmf: wifi@1 {
     80		reg = <1>;
     81		compatible = "brcm,bcm4329-fmac";
     82		interrupt-parent = <&gpio1>;
     83		interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
     84		interrupt-names = "host-wake";
     85	};
     86};
     87
     88&wdog1 {
     89	status = "okay";
     90};
     91
     92&iomuxc {
     93	pinctrl_gpmi_nand: gpmi-nand {
     94		fsl,pins = <
     95			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
     96			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
     97			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
     98			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb000
     99			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
    100			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
    101			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
    102			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
    103			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
    104			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
    105			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
    106			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
    107			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
    108			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
    109			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
    110		>;
    111	};
    112
    113	pinctrl_uart3: uart3grp {
    114		fsl,pins = <
    115			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
    116			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b099
    117			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
    118			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b099
    119			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x79		/* BT_REG_ON */
    120			MX6UL_PAD_SD1_CLK__GPIO2_IO17		0x100b1		/* BT_DEV_WAKE out */
    121			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x1b0b0		/* BT_HOST_WAKE in */
    122		>;
    123	};
    124
    125	pinctrl_uart4: uart4grp {
    126		fsl,pins = <
    127			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
    128			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
    129		>;
    130	};
    131
    132	pinctrl_wlan: wlangrp {
    133		fsl,pins = <
    134			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
    135			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10059
    136			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
    137			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
    138			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
    139			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
    140			MX6UL_PAD_SD1_DATA3__GPIO2_IO21		0x79		/* WL_REG_ON */
    141			MX6UL_PAD_UART2_CTS_B__GPIO1_IO22	0x100b1		/* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
    142			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x1b0b1		/* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
    143			MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT	0x4001b031	/* OSC 32Khz wifi clk in */
    144		>;
    145	};
    146};