imx7s.dtsi (34480B)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 #cooling-cells = <2>; 81 nvmem-cells = <&fuse_grade>; 82 nvmem-cell-names = "speed_grade"; 83 }; 84 }; 85 86 cpu0_opp_table: opp-table { 87 compatible = "operating-points-v2"; 88 opp-shared; 89 90 opp-792000000 { 91 opp-hz = /bits/ 64 <792000000>; 92 opp-microvolt = <1000000>; 93 clock-latency-ns = <150000>; 94 opp-supported-hw = <0xf>, <0xf>; 95 }; 96 }; 97 98 ckil: clock-cki { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32768>; 102 clock-output-names = "ckil"; 103 }; 104 105 osc: clock-osc { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <24000000>; 109 clock-output-names = "osc"; 110 }; 111 112 usbphynop1: usbphynop1 { 113 compatible = "usb-nop-xceiv"; 114 clocks = <&clks IMX7D_USB_PHY1_CLK>; 115 clock-names = "main_clk"; 116 #phy-cells = <0>; 117 }; 118 119 usbphynop3: usbphynop3 { 120 compatible = "usb-nop-xceiv"; 121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 122 clock-names = "main_clk"; 123 power-domains = <&pgc_hsic_phy>; 124 #phy-cells = <0>; 125 }; 126 127 pmu { 128 compatible = "arm,cortex-a7-pmu"; 129 interrupt-parent = <&gpc>; 130 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&cpu0>; 132 }; 133 134 replicator { 135 /* 136 * non-configurable replicators don't show up on the 137 * AMBA bus. As such no need to add "arm,primecell" 138 */ 139 compatible = "arm,coresight-static-replicator"; 140 141 out-ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 /* replicator output ports */ 145 port@0 { 146 reg = <0>; 147 replicator_out_port0: endpoint { 148 remote-endpoint = <&tpiu_in_port>; 149 }; 150 }; 151 152 port@1 { 153 reg = <1>; 154 replicator_out_port1: endpoint { 155 remote-endpoint = <&etr_in_port>; 156 }; 157 }; 158 }; 159 160 in-ports { 161 port { 162 replicator_in_port0: endpoint { 163 remote-endpoint = <&etf_out_port>; 164 }; 165 }; 166 }; 167 }; 168 169 timer { 170 compatible = "arm,armv7-timer"; 171 arm,cpu-registers-not-fw-configured; 172 interrupt-parent = <&intc>; 173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 177 }; 178 179 soc { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 compatible = "simple-bus"; 183 interrupt-parent = <&gpc>; 184 ranges; 185 186 funnel@30041000 { 187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 188 reg = <0x30041000 0x1000>; 189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 190 clock-names = "apb_pclk"; 191 192 ca_funnel_in_ports: in-ports { 193 port { 194 ca_funnel_in_port0: endpoint { 195 remote-endpoint = <&etm0_out_port>; 196 }; 197 }; 198 199 /* the other input ports are not connect to anything */ 200 }; 201 202 out-ports { 203 port { 204 ca_funnel_out_port0: endpoint { 205 remote-endpoint = <&hugo_funnel_in_port0>; 206 }; 207 }; 208 209 }; 210 }; 211 212 etm@3007c000 { 213 compatible = "arm,coresight-etm3x", "arm,primecell"; 214 reg = <0x3007c000 0x1000>; 215 cpu = <&cpu0>; 216 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 217 clock-names = "apb_pclk"; 218 219 out-ports { 220 port { 221 etm0_out_port: endpoint { 222 remote-endpoint = <&ca_funnel_in_port0>; 223 }; 224 }; 225 }; 226 }; 227 228 funnel@30083000 { 229 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 230 reg = <0x30083000 0x1000>; 231 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 232 clock-names = "apb_pclk"; 233 234 in-ports { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 port@0 { 239 reg = <0>; 240 hugo_funnel_in_port0: endpoint { 241 remote-endpoint = <&ca_funnel_out_port0>; 242 }; 243 }; 244 245 port@1 { 246 reg = <1>; 247 hugo_funnel_in_port1: endpoint { 248 /* M4 input */ 249 }; 250 }; 251 /* the other input ports are not connect to anything */ 252 }; 253 254 out-ports { 255 port { 256 hugo_funnel_out_port0: endpoint { 257 remote-endpoint = <&etf_in_port>; 258 }; 259 }; 260 }; 261 }; 262 263 etf@30084000 { 264 compatible = "arm,coresight-tmc", "arm,primecell"; 265 reg = <0x30084000 0x1000>; 266 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 267 clock-names = "apb_pclk"; 268 269 in-ports { 270 port { 271 etf_in_port: endpoint { 272 remote-endpoint = <&hugo_funnel_out_port0>; 273 }; 274 }; 275 }; 276 277 out-ports { 278 port { 279 etf_out_port: endpoint { 280 remote-endpoint = <&replicator_in_port0>; 281 }; 282 }; 283 }; 284 }; 285 286 etr@30086000 { 287 compatible = "arm,coresight-tmc", "arm,primecell"; 288 reg = <0x30086000 0x1000>; 289 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 290 clock-names = "apb_pclk"; 291 292 in-ports { 293 port { 294 etr_in_port: endpoint { 295 remote-endpoint = <&replicator_out_port1>; 296 }; 297 }; 298 }; 299 }; 300 301 tpiu@30087000 { 302 compatible = "arm,coresight-tpiu", "arm,primecell"; 303 reg = <0x30087000 0x1000>; 304 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 305 clock-names = "apb_pclk"; 306 307 in-ports { 308 port { 309 tpiu_in_port: endpoint { 310 remote-endpoint = <&replicator_out_port0>; 311 }; 312 }; 313 }; 314 }; 315 316 intc: interrupt-controller@31001000 { 317 compatible = "arm,cortex-a7-gic"; 318 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 319 #interrupt-cells = <3>; 320 interrupt-controller; 321 interrupt-parent = <&intc>; 322 reg = <0x31001000 0x1000>, 323 <0x31002000 0x2000>, 324 <0x31004000 0x2000>, 325 <0x31006000 0x2000>; 326 }; 327 328 aips1: bus@30000000 { 329 compatible = "fsl,aips-bus", "simple-bus"; 330 #address-cells = <1>; 331 #size-cells = <1>; 332 reg = <0x30000000 0x400000>; 333 ranges; 334 335 gpio1: gpio@30200000 { 336 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 337 reg = <0x30200000 0x10000>; 338 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 339 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 340 gpio-controller; 341 #gpio-cells = <2>; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 345 }; 346 347 gpio2: gpio@30210000 { 348 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 349 reg = <0x30210000 0x10000>; 350 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 gpio-ranges = <&iomuxc 0 13 32>; 357 }; 358 359 gpio3: gpio@30220000 { 360 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 361 reg = <0x30220000 0x10000>; 362 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 gpio-ranges = <&iomuxc 0 45 29>; 369 }; 370 371 gpio4: gpio@30230000 { 372 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 373 reg = <0x30230000 0x10000>; 374 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 gpio-ranges = <&iomuxc 0 74 24>; 381 }; 382 383 gpio5: gpio@30240000 { 384 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 385 reg = <0x30240000 0x10000>; 386 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 gpio-ranges = <&iomuxc 0 98 18>; 393 }; 394 395 gpio6: gpio@30250000 { 396 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 397 reg = <0x30250000 0x10000>; 398 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 gpio-ranges = <&iomuxc 0 116 23>; 405 }; 406 407 gpio7: gpio@30260000 { 408 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 409 reg = <0x30260000 0x10000>; 410 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 gpio-ranges = <&iomuxc 0 139 16>; 417 }; 418 419 wdog1: watchdog@30280000 { 420 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 421 reg = <0x30280000 0x10000>; 422 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 424 }; 425 426 wdog2: watchdog@30290000 { 427 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 428 reg = <0x30290000 0x10000>; 429 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 431 status = "disabled"; 432 }; 433 434 wdog3: watchdog@302a0000 { 435 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 436 reg = <0x302a0000 0x10000>; 437 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 439 status = "disabled"; 440 }; 441 442 wdog4: watchdog@302b0000 { 443 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 444 reg = <0x302b0000 0x10000>; 445 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 447 status = "disabled"; 448 }; 449 450 iomuxc_lpsr: pinctrl@302c0000 { 451 compatible = "fsl,imx7d-iomuxc-lpsr"; 452 reg = <0x302c0000 0x10000>; 453 fsl,input-sel = <&iomuxc>; 454 }; 455 456 gpt1: timer@302d0000 { 457 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 458 reg = <0x302d0000 0x10000>; 459 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 461 <&clks IMX7D_GPT1_ROOT_CLK>; 462 clock-names = "ipg", "per"; 463 }; 464 465 gpt2: timer@302e0000 { 466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 467 reg = <0x302e0000 0x10000>; 468 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 470 <&clks IMX7D_GPT2_ROOT_CLK>; 471 clock-names = "ipg", "per"; 472 status = "disabled"; 473 }; 474 475 gpt3: timer@302f0000 { 476 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 477 reg = <0x302f0000 0x10000>; 478 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 480 <&clks IMX7D_GPT3_ROOT_CLK>; 481 clock-names = "ipg", "per"; 482 status = "disabled"; 483 }; 484 485 gpt4: timer@30300000 { 486 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 487 reg = <0x30300000 0x10000>; 488 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 490 <&clks IMX7D_GPT4_ROOT_CLK>; 491 clock-names = "ipg", "per"; 492 status = "disabled"; 493 }; 494 495 kpp: keypad@30320000 { 496 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 497 reg = <0x30320000 0x10000>; 498 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 500 status = "disabled"; 501 }; 502 503 iomuxc: pinctrl@30330000 { 504 compatible = "fsl,imx7d-iomuxc"; 505 reg = <0x30330000 0x10000>; 506 }; 507 508 gpr: iomuxc-gpr@30340000 { 509 compatible = "fsl,imx7d-iomuxc-gpr", 510 "fsl,imx6q-iomuxc-gpr", "syscon", 511 "simple-mfd"; 512 reg = <0x30340000 0x10000>; 513 514 mux: mux-controller { 515 compatible = "mmio-mux"; 516 #mux-control-cells = <0>; 517 mux-reg-masks = <0x14 0x00000010>; 518 }; 519 520 video_mux: csi-mux { 521 compatible = "video-mux"; 522 mux-controls = <&mux 0>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 527 port@0 { 528 reg = <0>; 529 }; 530 531 port@1 { 532 reg = <1>; 533 534 csi_mux_from_mipi_vc0: endpoint { 535 remote-endpoint = <&mipi_vc0_to_csi_mux>; 536 }; 537 }; 538 539 port@2 { 540 reg = <2>; 541 542 csi_mux_to_csi: endpoint { 543 remote-endpoint = <&csi_from_csi_mux>; 544 }; 545 }; 546 }; 547 }; 548 549 ocotp: efuse@30350000 { 550 #address-cells = <1>; 551 #size-cells = <1>; 552 compatible = "fsl,imx7d-ocotp", "syscon"; 553 reg = <0x30350000 0x10000>; 554 clocks = <&clks IMX7D_OCOTP_CLK>; 555 556 tempmon_calib: calib@3c { 557 reg = <0x3c 0x4>; 558 }; 559 560 fuse_grade: fuse-grade@10 { 561 reg = <0x10 0x4>; 562 }; 563 }; 564 565 anatop: anatop@30360000 { 566 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 567 "syscon", "simple-mfd"; 568 reg = <0x30360000 0x10000>; 569 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 571 572 reg_1p0d: regulator-vdd1p0d { 573 compatible = "fsl,anatop-regulator"; 574 regulator-name = "vdd1p0d"; 575 regulator-min-microvolt = <800000>; 576 regulator-max-microvolt = <1200000>; 577 anatop-reg-offset = <0x210>; 578 anatop-vol-bit-shift = <8>; 579 anatop-vol-bit-width = <5>; 580 anatop-min-bit-val = <8>; 581 anatop-min-voltage = <800000>; 582 anatop-max-voltage = <1200000>; 583 anatop-enable-bit = <0>; 584 }; 585 586 reg_1p2: regulator-vdd1p2 { 587 compatible = "fsl,anatop-regulator"; 588 regulator-name = "vdd1p2"; 589 regulator-min-microvolt = <1100000>; 590 regulator-max-microvolt = <1300000>; 591 anatop-reg-offset = <0x220>; 592 anatop-vol-bit-shift = <8>; 593 anatop-vol-bit-width = <5>; 594 anatop-min-bit-val = <0x14>; 595 anatop-min-voltage = <1100000>; 596 anatop-max-voltage = <1300000>; 597 anatop-enable-bit = <0>; 598 }; 599 600 tempmon: tempmon { 601 compatible = "fsl,imx7d-tempmon"; 602 interrupt-parent = <&gpc>; 603 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 604 fsl,tempmon = <&anatop>; 605 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 606 nvmem-cell-names = "calib", "temp_grade"; 607 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 608 }; 609 }; 610 611 snvs: snvs@30370000 { 612 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 613 reg = <0x30370000 0x10000>; 614 615 snvs_rtc: snvs-rtc-lp { 616 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 617 regmap = <&snvs>; 618 offset = <0x34>; 619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&clks IMX7D_SNVS_CLK>; 622 clock-names = "snvs-rtc"; 623 }; 624 625 snvs_pwrkey: snvs-powerkey { 626 compatible = "fsl,sec-v4.0-pwrkey"; 627 regmap = <&snvs>; 628 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&clks IMX7D_SNVS_CLK>; 630 clock-names = "snvs-pwrkey"; 631 linux,keycode = <KEY_POWER>; 632 wakeup-source; 633 status = "disabled"; 634 }; 635 }; 636 637 clks: clock-controller@30380000 { 638 compatible = "fsl,imx7d-ccm"; 639 reg = <0x30380000 0x10000>; 640 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 642 #clock-cells = <1>; 643 clocks = <&ckil>, <&osc>; 644 clock-names = "ckil", "osc"; 645 }; 646 647 src: reset-controller@30390000 { 648 compatible = "fsl,imx7d-src", "syscon"; 649 reg = <0x30390000 0x10000>; 650 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 651 #reset-cells = <1>; 652 }; 653 654 gpc: gpc@303a0000 { 655 compatible = "fsl,imx7d-gpc"; 656 reg = <0x303a0000 0x10000>; 657 interrupt-controller; 658 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 659 #interrupt-cells = <3>; 660 interrupt-parent = <&intc>; 661 #power-domain-cells = <1>; 662 663 pgc { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 667 pgc_mipi_phy: power-domain@0 { 668 #power-domain-cells = <0>; 669 reg = <0>; 670 power-supply = <®_1p0d>; 671 }; 672 673 pgc_pcie_phy: power-domain@1 { 674 #power-domain-cells = <0>; 675 reg = <1>; 676 power-supply = <®_1p0d>; 677 }; 678 679 pgc_hsic_phy: power-domain@2 { 680 #power-domain-cells = <0>; 681 reg = <2>; 682 power-supply = <®_1p2>; 683 }; 684 }; 685 }; 686 }; 687 688 aips2: bus@30400000 { 689 compatible = "fsl,aips-bus", "simple-bus"; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 reg = <0x30400000 0x400000>; 693 ranges; 694 695 adc1: adc@30610000 { 696 compatible = "fsl,imx7d-adc"; 697 reg = <0x30610000 0x10000>; 698 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 700 clock-names = "adc"; 701 #io-channel-cells = <1>; 702 status = "disabled"; 703 }; 704 705 adc2: adc@30620000 { 706 compatible = "fsl,imx7d-adc"; 707 reg = <0x30620000 0x10000>; 708 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 710 clock-names = "adc"; 711 #io-channel-cells = <1>; 712 status = "disabled"; 713 }; 714 715 ecspi4: spi@30630000 { 716 #address-cells = <1>; 717 #size-cells = <0>; 718 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 719 reg = <0x30630000 0x10000>; 720 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 722 <&clks IMX7D_ECSPI4_ROOT_CLK>; 723 clock-names = "ipg", "per"; 724 status = "disabled"; 725 }; 726 727 ftm1: pwm@30640000 { 728 compatible = "fsl,vf610-ftm-pwm"; 729 reg = <0x30640000 0x10000>; 730 #pwm-cells = <3>; 731 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 732 clock-names = "ftm_sys", "ftm_ext", 733 "ftm_fix", "ftm_cnt_clk_en"; 734 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 735 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 736 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 737 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; 738 status = "disabled"; 739 }; 740 741 ftm2: pwm@30650000 { 742 compatible = "fsl,vf610-ftm-pwm"; 743 reg = <0x30650000 0x10000>; 744 #pwm-cells = <3>; 745 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 746 clock-names = "ftm_sys", "ftm_ext", 747 "ftm_fix", "ftm_cnt_clk_en"; 748 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 749 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 750 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 751 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; 752 status = "disabled"; 753 }; 754 755 pwm1: pwm@30660000 { 756 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 757 reg = <0x30660000 0x10000>; 758 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 760 <&clks IMX7D_PWM1_ROOT_CLK>; 761 clock-names = "ipg", "per"; 762 #pwm-cells = <3>; 763 status = "disabled"; 764 }; 765 766 pwm2: pwm@30670000 { 767 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 768 reg = <0x30670000 0x10000>; 769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 771 <&clks IMX7D_PWM2_ROOT_CLK>; 772 clock-names = "ipg", "per"; 773 #pwm-cells = <3>; 774 status = "disabled"; 775 }; 776 777 pwm3: pwm@30680000 { 778 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 779 reg = <0x30680000 0x10000>; 780 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 782 <&clks IMX7D_PWM3_ROOT_CLK>; 783 clock-names = "ipg", "per"; 784 #pwm-cells = <3>; 785 status = "disabled"; 786 }; 787 788 pwm4: pwm@30690000 { 789 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 790 reg = <0x30690000 0x10000>; 791 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 793 <&clks IMX7D_PWM4_ROOT_CLK>; 794 clock-names = "ipg", "per"; 795 #pwm-cells = <3>; 796 status = "disabled"; 797 }; 798 799 csi: csi@30710000 { 800 compatible = "fsl,imx7-csi"; 801 reg = <0x30710000 0x10000>; 802 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clks IMX7D_CLK_DUMMY>, 804 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 805 <&clks IMX7D_CLK_DUMMY>; 806 clock-names = "axi", "mclk", "dcic"; 807 status = "disabled"; 808 809 port { 810 csi_from_csi_mux: endpoint { 811 remote-endpoint = <&csi_mux_to_csi>; 812 }; 813 }; 814 }; 815 816 lcdif: lcdif@30730000 { 817 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 818 reg = <0x30730000 0x10000>; 819 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 821 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 822 clock-names = "pix", "axi"; 823 status = "disabled"; 824 }; 825 826 mipi_csi: mipi-csi@30750000 { 827 compatible = "fsl,imx7-mipi-csi2"; 828 reg = <0x30750000 0x10000>; 829 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 831 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 832 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 833 clock-names = "pclk", "wrap", "phy"; 834 power-domains = <&pgc_mipi_phy>; 835 phy-supply = <®_1p0d>; 836 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 837 status = "disabled"; 838 839 ports { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 port@0 { 844 reg = <0>; 845 }; 846 847 port@1 { 848 reg = <1>; 849 850 mipi_vc0_to_csi_mux: endpoint { 851 remote-endpoint = <&csi_mux_from_mipi_vc0>; 852 }; 853 }; 854 }; 855 }; 856 }; 857 858 aips3: bus@30800000 { 859 compatible = "fsl,aips-bus", "simple-bus"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 reg = <0x30800000 0x400000>; 863 ranges; 864 865 spba-bus@30800000 { 866 compatible = "fsl,spba-bus", "simple-bus"; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 reg = <0x30800000 0x100000>; 870 ranges; 871 872 ecspi1: spi@30820000 { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 876 reg = <0x30820000 0x10000>; 877 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 879 <&clks IMX7D_ECSPI1_ROOT_CLK>; 880 clock-names = "ipg", "per"; 881 status = "disabled"; 882 }; 883 884 ecspi2: spi@30830000 { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 888 reg = <0x30830000 0x10000>; 889 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 891 <&clks IMX7D_ECSPI2_ROOT_CLK>; 892 clock-names = "ipg", "per"; 893 status = "disabled"; 894 }; 895 896 ecspi3: spi@30840000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 900 reg = <0x30840000 0x10000>; 901 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 903 <&clks IMX7D_ECSPI3_ROOT_CLK>; 904 clock-names = "ipg", "per"; 905 status = "disabled"; 906 }; 907 908 uart1: serial@30860000 { 909 compatible = "fsl,imx7d-uart", 910 "fsl,imx6q-uart"; 911 reg = <0x30860000 0x10000>; 912 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 914 <&clks IMX7D_UART1_ROOT_CLK>; 915 clock-names = "ipg", "per"; 916 status = "disabled"; 917 }; 918 919 uart2: serial@30890000 { 920 compatible = "fsl,imx7d-uart", 921 "fsl,imx6q-uart"; 922 reg = <0x30890000 0x10000>; 923 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 925 <&clks IMX7D_UART2_ROOT_CLK>; 926 clock-names = "ipg", "per"; 927 status = "disabled"; 928 }; 929 930 uart3: serial@30880000 { 931 compatible = "fsl,imx7d-uart", 932 "fsl,imx6q-uart"; 933 reg = <0x30880000 0x10000>; 934 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 936 <&clks IMX7D_UART3_ROOT_CLK>; 937 clock-names = "ipg", "per"; 938 status = "disabled"; 939 }; 940 941 sai1: sai@308a0000 { 942 #sound-dai-cells = <0>; 943 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 944 reg = <0x308a0000 0x10000>; 945 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 947 <&clks IMX7D_SAI1_ROOT_CLK>, 948 <&clks IMX7D_CLK_DUMMY>, 949 <&clks IMX7D_CLK_DUMMY>; 950 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 951 dma-names = "rx", "tx"; 952 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 953 status = "disabled"; 954 }; 955 956 sai2: sai@308b0000 { 957 #sound-dai-cells = <0>; 958 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 959 reg = <0x308b0000 0x10000>; 960 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 962 <&clks IMX7D_SAI2_ROOT_CLK>, 963 <&clks IMX7D_CLK_DUMMY>, 964 <&clks IMX7D_CLK_DUMMY>; 965 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 966 dma-names = "rx", "tx"; 967 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 968 status = "disabled"; 969 }; 970 971 sai3: sai@308c0000 { 972 #sound-dai-cells = <0>; 973 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 974 reg = <0x308c0000 0x10000>; 975 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 977 <&clks IMX7D_SAI3_ROOT_CLK>, 978 <&clks IMX7D_CLK_DUMMY>, 979 <&clks IMX7D_CLK_DUMMY>; 980 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 981 dma-names = "rx", "tx"; 982 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 983 status = "disabled"; 984 }; 985 }; 986 987 crypto: crypto@30900000 { 988 compatible = "fsl,sec-v4.0"; 989 #address-cells = <1>; 990 #size-cells = <1>; 991 reg = <0x30900000 0x40000>; 992 ranges = <0 0x30900000 0x40000>; 993 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&clks IMX7D_CAAM_CLK>, 995 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 996 clock-names = "ipg", "aclk"; 997 998 sec_jr0: jr@1000 { 999 compatible = "fsl,sec-v4.0-job-ring"; 1000 reg = <0x1000 0x1000>; 1001 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1002 }; 1003 1004 sec_jr1: jr@2000 { 1005 compatible = "fsl,sec-v4.0-job-ring"; 1006 reg = <0x2000 0x1000>; 1007 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1008 }; 1009 1010 sec_jr2: jr@3000 { 1011 compatible = "fsl,sec-v4.0-job-ring"; 1012 reg = <0x3000 0x1000>; 1013 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1014 }; 1015 }; 1016 1017 flexcan1: can@30a00000 { 1018 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1019 reg = <0x30a00000 0x10000>; 1020 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&clks IMX7D_CLK_DUMMY>, 1022 <&clks IMX7D_CAN1_ROOT_CLK>; 1023 clock-names = "ipg", "per"; 1024 fsl,stop-mode = <&gpr 0x10 1>; 1025 status = "disabled"; 1026 }; 1027 1028 flexcan2: can@30a10000 { 1029 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1030 reg = <0x30a10000 0x10000>; 1031 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX7D_CLK_DUMMY>, 1033 <&clks IMX7D_CAN2_ROOT_CLK>; 1034 clock-names = "ipg", "per"; 1035 fsl,stop-mode = <&gpr 0x10 2>; 1036 status = "disabled"; 1037 }; 1038 1039 i2c1: i2c@30a20000 { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1043 reg = <0x30a20000 0x10000>; 1044 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1046 status = "disabled"; 1047 }; 1048 1049 i2c2: i2c@30a30000 { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1053 reg = <0x30a30000 0x10000>; 1054 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c3: i2c@30a40000 { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1063 reg = <0x30a40000 0x10000>; 1064 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c4: i2c@30a50000 { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1073 reg = <0x30a50000 0x10000>; 1074 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1076 status = "disabled"; 1077 }; 1078 1079 uart4: serial@30a60000 { 1080 compatible = "fsl,imx7d-uart", 1081 "fsl,imx6q-uart"; 1082 reg = <0x30a60000 0x10000>; 1083 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1085 <&clks IMX7D_UART4_ROOT_CLK>; 1086 clock-names = "ipg", "per"; 1087 status = "disabled"; 1088 }; 1089 1090 uart5: serial@30a70000 { 1091 compatible = "fsl,imx7d-uart", 1092 "fsl,imx6q-uart"; 1093 reg = <0x30a70000 0x10000>; 1094 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1096 <&clks IMX7D_UART5_ROOT_CLK>; 1097 clock-names = "ipg", "per"; 1098 status = "disabled"; 1099 }; 1100 1101 uart6: serial@30a80000 { 1102 compatible = "fsl,imx7d-uart", 1103 "fsl,imx6q-uart"; 1104 reg = <0x30a80000 0x10000>; 1105 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1107 <&clks IMX7D_UART6_ROOT_CLK>; 1108 clock-names = "ipg", "per"; 1109 status = "disabled"; 1110 }; 1111 1112 uart7: serial@30a90000 { 1113 compatible = "fsl,imx7d-uart", 1114 "fsl,imx6q-uart"; 1115 reg = <0x30a90000 0x10000>; 1116 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1118 <&clks IMX7D_UART7_ROOT_CLK>; 1119 clock-names = "ipg", "per"; 1120 status = "disabled"; 1121 }; 1122 1123 mu0a: mailbox@30aa0000 { 1124 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1125 reg = <0x30aa0000 0x10000>; 1126 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1128 #mbox-cells = <2>; 1129 status = "disabled"; 1130 }; 1131 1132 mu0b: mailbox@30ab0000 { 1133 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1134 reg = <0x30ab0000 0x10000>; 1135 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1137 #mbox-cells = <2>; 1138 fsl,mu-side-b; 1139 status = "disabled"; 1140 }; 1141 1142 usbotg1: usb@30b10000 { 1143 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1144 reg = <0x30b10000 0x200>; 1145 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1147 fsl,usbphy = <&usbphynop1>; 1148 fsl,usbmisc = <&usbmisc1 0>; 1149 phy-clkgate-delay-us = <400>; 1150 status = "disabled"; 1151 }; 1152 1153 usbh: usb@30b30000 { 1154 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1155 reg = <0x30b30000 0x200>; 1156 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1158 fsl,usbphy = <&usbphynop3>; 1159 fsl,usbmisc = <&usbmisc3 0>; 1160 phy_type = "hsic"; 1161 dr_mode = "host"; 1162 phy-clkgate-delay-us = <400>; 1163 status = "disabled"; 1164 }; 1165 1166 usbmisc1: usbmisc@30b10200 { 1167 #index-cells = <1>; 1168 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1169 reg = <0x30b10200 0x200>; 1170 }; 1171 1172 usbmisc3: usbmisc@30b30200 { 1173 #index-cells = <1>; 1174 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1175 reg = <0x30b30200 0x200>; 1176 }; 1177 1178 usdhc1: mmc@30b40000 { 1179 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1180 reg = <0x30b40000 0x10000>; 1181 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1183 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1184 <&clks IMX7D_USDHC1_ROOT_CLK>; 1185 clock-names = "ipg", "ahb", "per"; 1186 bus-width = <4>; 1187 status = "disabled"; 1188 }; 1189 1190 usdhc2: mmc@30b50000 { 1191 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1192 reg = <0x30b50000 0x10000>; 1193 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1195 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1196 <&clks IMX7D_USDHC2_ROOT_CLK>; 1197 clock-names = "ipg", "ahb", "per"; 1198 bus-width = <4>; 1199 status = "disabled"; 1200 }; 1201 1202 usdhc3: mmc@30b60000 { 1203 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1204 reg = <0x30b60000 0x10000>; 1205 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1207 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1208 <&clks IMX7D_USDHC3_ROOT_CLK>; 1209 clock-names = "ipg", "ahb", "per"; 1210 bus-width = <4>; 1211 status = "disabled"; 1212 }; 1213 1214 qspi: spi@30bb0000 { 1215 compatible = "fsl,imx7d-qspi"; 1216 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1217 reg-names = "QuadSPI", "QuadSPI-memory"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1222 <&clks IMX7D_QSPI_ROOT_CLK>; 1223 clock-names = "qspi_en", "qspi"; 1224 status = "disabled"; 1225 }; 1226 1227 sdma: sdma@30bd0000 { 1228 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1229 reg = <0x30bd0000 0x10000>; 1230 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1232 <&clks IMX7D_SDMA_CORE_CLK>; 1233 clock-names = "ipg", "ahb"; 1234 #dma-cells = <3>; 1235 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1236 }; 1237 1238 fec1: ethernet@30be0000 { 1239 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1240 reg = <0x30be0000 0x10000>; 1241 interrupt-names = "int0", "int1", "int2", "pps"; 1242 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1247 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1248 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1249 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1250 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1251 clock-names = "ipg", "ahb", "ptp", 1252 "enet_clk_ref", "enet_out"; 1253 fsl,num-tx-queues = <3>; 1254 fsl,num-rx-queues = <3>; 1255 fsl,stop-mode = <&gpr 0x10 3>; 1256 status = "disabled"; 1257 }; 1258 }; 1259 1260 dma_apbh: dma-apbh@33000000 { 1261 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1262 reg = <0x33000000 0x2000>; 1263 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1267 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1268 #dma-cells = <1>; 1269 dma-channels = <4>; 1270 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1271 }; 1272 1273 gpmi: nand-controller@33002000{ 1274 compatible = "fsl,imx7d-gpmi-nand"; 1275 #address-cells = <1>; 1276 #size-cells = <1>; 1277 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1278 reg-names = "gpmi-nand", "bch"; 1279 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1280 interrupt-names = "bch"; 1281 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1282 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1283 clock-names = "gpmi_io", "gpmi_bch_apb"; 1284 dmas = <&dma_apbh 0>; 1285 dma-names = "rx-tx"; 1286 status = "disabled"; 1287 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1288 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1289 }; 1290 }; 1291};