cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel-ixp42x-adi-coyote.dts (2687B)

      1// SPDX-License-Identifier: ISC
      2/*
      3 * Device Tree file for ADI Engineering Coyote platform.
      4 * Derived from boardfiles written by MontaVista software.
      5 * Ethernet set-up from OpenWrt.
      6 */
      7
      8/dts-v1/;
      9
     10#include "intel-ixp42x.dtsi"
     11#include <dt-bindings/input/input.h>
     12
     13/ {
     14	model = "ADI Engineering Coyote reference design";
     15	compatible = "adieng,coyote", "intel,ixp42x";
     16	#address-cells = <1>;
     17	#size-cells = <1>;
     18
     19	memory@0 {
     20		/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
     21		device_type = "memory";
     22		reg = <0x00000000 0x01000000>;
     23	};
     24
     25	chosen {
     26		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
     27		stdout-path = "uart1:115200n8";
     28	};
     29
     30	aliases {
     31		/* These are switched around */
     32		serial0 = &uart1;
     33		serial1 = &uart0;
     34	};
     35
     36	soc {
     37		bus@c4000000 {
     38			flash@0,0 {
     39				compatible = "intel,ixp4xx-flash", "cfi-flash";
     40				bank-width = <2>;
     41				/*
     42				 * 32 MB of Flash in 128 0x20000 sized blocks
     43				 * mapped in at CS0 and CS1
     44				 */
     45				reg = <0 0x00000000 0x2000000>;
     46
     47				/* Configure expansion bus to allow writes */
     48				intel,ixp4xx-eb-write-enable = <1>;
     49
     50				partitions {
     51					compatible = "redboot-fis";
     52					/* CHECKME: guess this is Redboot FIS */
     53					fis-index-block = <0x1ff>;
     54				};
     55			};
     56		};
     57
     58		pci@c0000000 {
     59			status = "ok";
     60
     61			/*
     62			 * Taken from Coyote PCI boardfile.
     63			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
     64			 * each handling all IRQs.
     65			 */
     66			#interrupt-cells = <1>;
     67			interrupt-map-mask = <0xf800 0 0 7>;
     68			interrupt-map =
     69			/* IDSEL 1 */
     70			<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
     71			<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
     72			<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
     73			<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
     74			/* IDSEL 2 */
     75			<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
     76			<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
     77			<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
     78			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
     79		};
     80
     81		/* EthB */
     82		ethernet@c8009000 {
     83			status = "ok";
     84			queue-rx = <&qmgr 3>;
     85			queue-txready = <&qmgr 20>;
     86			phy-mode = "rgmii";
     87			phy-handle = <&phy5>;
     88
     89			mdio {
     90				#address-cells = <1>;
     91				#size-cells = <0>;
     92
     93				phy4: ethernet-phy@4 {
     94					reg = <4>;
     95				};
     96
     97				phy5: ethernet-phy@5 {
     98					reg = <5>;
     99				};
    100			};
    101		};
    102
    103		/* EthC */
    104		ethernet@c800a000 {
    105			status = "ok";
    106			queue-rx = <&qmgr 4>;
    107			queue-txready = <&qmgr 21>;
    108			phy-mode = "rgmii";
    109			phy-handle = <&phy4>;
    110		};
    111	};
    112};