cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel-ixp42x-iomega-nas100d.dts (3183B)

      1// SPDX-License-Identifier: ISC
      2/*
      3 * Device Tree file for Iomega NAS 100D
      4 */
      5
      6/dts-v1/;
      7
      8#include "intel-ixp42x.dtsi"
      9#include <dt-bindings/input/input.h>
     10
     11/ {
     12	model = "Iomega NAS 100D";
     13	compatible = "iom,nas-100d", "intel,ixp42x";
     14	#address-cells = <1>;
     15	#size-cells = <1>;
     16
     17	memory@0 {
     18		/* 64 MB SDRAM */
     19		device_type = "memory";
     20		reg = <0x00000000 0x4000000>;
     21	};
     22
     23	chosen {
     24		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
     25		stdout-path = "uart0:115200n8";
     26	};
     27
     28	aliases {
     29		serial0 = &uart0;
     30	};
     31
     32	leds {
     33		compatible = "gpio-leds";
     34		led-wlan {
     35			label = "nas100d:red:wlan";
     36			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
     37			default-state = "on";
     38			/* We don't have WLAN trigger in the kernel (yet) */
     39			linux,default-trigger = "netdev";
     40		};
     41		led-disk {
     42			label = "nas100d:red:disk";
     43			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
     44			default-state = "on";
     45			linux,default-trigger = "disk-activity";
     46		};
     47		led-power {
     48			label = "nas100d:red:power";
     49			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
     50			default-state = "on";
     51			linux,default-trigger = "heartbeat";
     52		};
     53	};
     54
     55	gpio_keys {
     56		compatible = "gpio-keys";
     57
     58		button-power {
     59			wakeup-source;
     60			linux,code = <KEY_POWER>;
     61			label = "power";
     62			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
     63		};
     64		button-reset {
     65			wakeup-source;
     66			linux,code = <KEY_ESC>;
     67			label = "reset";
     68			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
     69		};
     70	};
     71
     72	i2c {
     73		compatible = "i2c-gpio";
     74		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
     75		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
     76		#address-cells = <1>;
     77		#size-cells = <0>;
     78
     79		rtc@51 {
     80			compatible = "nxp,pcf8563";
     81			reg = <0x51>;
     82		};
     83	};
     84
     85	gpio-poweroff {
     86		compatible = "gpio-poweroff";
     87		gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
     88		timeout-ms = <5000>;
     89	};
     90
     91	soc {
     92		bus@c4000000 {
     93			/* The first 16MB region at CS0 on the expansion bus */
     94			flash@0,0 {
     95				compatible = "intel,ixp4xx-flash", "cfi-flash";
     96				bank-width = <2>;
     97				/*
     98				 * 8 MB of Flash in 0x20000 byte blocks
     99				 * mapped in at CS0.
    100				 */
    101				reg = <0 0x00000000 0x800000>;
    102
    103				partitions {
    104					compatible = "redboot-fis";
    105					/* Eraseblock at 0x7e0000 */
    106					fis-index-block = <0x3f>;
    107				};
    108			};
    109		};
    110
    111		pci@c0000000 {
    112			status = "ok";
    113
    114			/*
    115			 * Taken from NAS 100D PCI boardfile (nas100d-pci.c)
    116			 * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
    117			 */
    118			#interrupt-cells = <1>;
    119			interrupt-map-mask = <0xf800 0 0 7>;
    120			interrupt-map =
    121			/* IDSEL 1 */
    122			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
    123			/* IDSEL 2 */
    124			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
    125			/* IDSEL 3 */
    126			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
    127			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
    128			<0x1800 0 0 3 &gpio0 7  IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */
    129		};
    130
    131		ethernet@c8009000 {
    132			status = "ok";
    133			queue-rx = <&qmgr 3>;
    134			queue-txready = <&qmgr 20>;
    135			phy-mode = "rgmii";
    136			phy-handle = <&phy0>;
    137
    138			mdio {
    139				#address-cells = <1>;
    140				#size-cells = <0>;
    141
    142				phy0: ethernet-phy@0 {
    143					reg = <0>;
    144				};
    145			};
    146		};
    147	};
    148};