cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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keystone-k2hk-evm.dts (4277B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Keystone 2 Kepler/Hawking EVM device tree
      4 *
      5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
      6 */
      7/dts-v1/;
      8
      9#include "keystone.dtsi"
     10#include "keystone-k2hk.dtsi"
     11
     12/ {
     13	compatible =  "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
     14	model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
     15
     16	reserved-memory {
     17		#address-cells = <2>;
     18		#size-cells = <2>;
     19		ranges;
     20
     21		dsp_common_memory: dsp-common-memory@81f800000 {
     22			compatible = "shared-dma-pool";
     23			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
     24			reusable;
     25			status = "okay";
     26		};
     27	};
     28
     29	leds {
     30		compatible = "gpio-leds";
     31		debug1_1 {
     32			label = "keystone:green:debug1";
     33			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
     34		};
     35
     36		debug1_2 {
     37			label = "keystone:red:debug1";
     38			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
     39		};
     40
     41		debug2 {
     42			label = "keystone:blue:debug2";
     43			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
     44		};
     45
     46		debug3 {
     47			label = "keystone:blue:debug3";
     48			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
     49		};
     50	};
     51};
     52
     53&soc0 {
     54		clocks {
     55			refclksys: refclksys {
     56				#clock-cells = <0>;
     57				compatible = "fixed-clock";
     58				clock-frequency = <122880000>;
     59				clock-output-names = "refclk-sys";
     60			};
     61
     62			refclkpass: refclkpass {
     63				#clock-cells = <0>;
     64				compatible = "fixed-clock";
     65				clock-frequency = <122880000>;
     66				clock-output-names = "refclk-pass";
     67			};
     68
     69			refclkarm: refclkarm {
     70				#clock-cells = <0>;
     71				compatible = "fixed-clock";
     72				clock-frequency = <125000000>;
     73				clock-output-names = "refclk-arm";
     74			};
     75
     76			refclkddr3a: refclkddr3a {
     77				#clock-cells = <0>;
     78				compatible = "fixed-clock";
     79				clock-frequency = <100000000>;
     80				clock-output-names = "refclk-ddr3a";
     81			};
     82
     83			refclkddr3b: refclkddr3b {
     84				#clock-cells = <0>;
     85				compatible = "fixed-clock";
     86				clock-frequency = <100000000>;
     87				clock-output-names = "refclk-ddr3b";
     88			};
     89		};
     90};
     91
     92&usb_phy {
     93	status = "okay";
     94};
     95
     96&keystone_usb0 {
     97	status = "okay";
     98};
     99
    100&usb0 {
    101	dr_mode = "host";
    102};
    103
    104&aemif {
    105	cs0 {
    106		#address-cells = <2>;
    107		#size-cells = <1>;
    108		clock-ranges;
    109		ranges;
    110
    111		ti,cs-chipselect = <0>;
    112		/* all timings in nanoseconds */
    113		ti,cs-min-turnaround-ns = <12>;
    114		ti,cs-read-hold-ns = <6>;
    115		ti,cs-read-strobe-ns = <23>;
    116		ti,cs-read-setup-ns = <9>;
    117		ti,cs-write-hold-ns = <8>;
    118		ti,cs-write-strobe-ns = <23>;
    119		ti,cs-write-setup-ns = <8>;
    120
    121		nand@0,0 {
    122			compatible = "ti,keystone-nand","ti,davinci-nand";
    123			#address-cells = <1>;
    124			#size-cells = <1>;
    125			reg = <0 0 0x4000000
    126			       1 0 0x0000100>;
    127
    128			ti,davinci-chipselect = <0>;
    129			ti,davinci-mask-ale = <0x2000>;
    130			ti,davinci-mask-cle = <0x4000>;
    131			ti,davinci-mask-chipsel = <0>;
    132			nand-ecc-mode = "hw";
    133			ti,davinci-ecc-bits = <4>;
    134			nand-on-flash-bbt;
    135
    136			partition@0 {
    137				label = "u-boot";
    138				reg = <0x0 0x100000>;
    139				read-only;
    140			};
    141
    142			partition@100000 {
    143				label = "params";
    144				reg = <0x100000 0x80000>;
    145				read-only;
    146			};
    147
    148			partition@180000 {
    149				label = "ubifs";
    150				reg = <0x180000 0x1fe80000>;
    151			};
    152		};
    153	};
    154};
    155
    156&i2c0 {
    157	dtt@50 {
    158		compatible = "atmel,24c1024";
    159		reg = <0x50>;
    160	};
    161};
    162
    163&spi0 {
    164	nor_flash: flash@0 {
    165		#address-cells = <1>;
    166		#size-cells = <1>;
    167		compatible = "micron,n25q128a11", "jedec,spi-nor";
    168		spi-max-frequency = <54000000>;
    169		m25p,fast-read;
    170		reg = <0>;
    171
    172		partition@0 {
    173			label = "u-boot-spl";
    174			reg = <0x0 0x80000>;
    175			read-only;
    176		};
    177
    178		partition@1 {
    179			label = "misc";
    180			reg = <0x80000 0xf80000>;
    181		};
    182	};
    183};
    184
    185&mdio {
    186	status = "ok";
    187	ethphy0: ethernet-phy@0 {
    188		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
    189		reg = <0>;
    190	};
    191
    192	ethphy1: ethernet-phy@1 {
    193		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
    194		reg = <1>;
    195	};
    196};
    197
    198&dsp0 {
    199	memory-region = <&dsp_common_memory>;
    200	status = "okay";
    201};
    202
    203&dsp1 {
    204	memory-region = <&dsp_common_memory>;
    205	status = "okay";
    206};
    207
    208&dsp2 {
    209	memory-region = <&dsp_common_memory>;
    210	status = "okay";
    211};
    212
    213&dsp3 {
    214	memory-region = <&dsp_common_memory>;
    215	status = "okay";
    216};
    217
    218&dsp4 {
    219	memory-region = <&dsp_common_memory>;
    220	status = "okay";
    221};
    222
    223&dsp5 {
    224	memory-region = <&dsp_common_memory>;
    225	status = "okay";
    226};
    227
    228&dsp6 {
    229	memory-region = <&dsp_common_memory>;
    230	status = "okay";
    231};
    232
    233&dsp7 {
    234	memory-region = <&dsp_common_memory>;
    235	status = "okay";
    236};