cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lan966x-kontron-kswitch-d10-mmt.dtsi (3033B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Common part of the device tree for the Kontron KSwitch D10 MMT
      4 */
      5
      6/dts-v1/;
      7#include "lan966x.dtsi"
      8#include "dt-bindings/phy/phy-lan966x-serdes.h"
      9
     10/ {
     11	aliases {
     12		serial0 = &usart0;
     13	};
     14
     15	chosen {
     16		stdout-path = "serial0:115200n8";
     17	};
     18
     19	gpio-restart {
     20		compatible = "gpio-restart";
     21		gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
     22		priority = <200>;
     23	};
     24};
     25
     26&flx0 {
     27	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
     28	status = "okay";
     29
     30	usart0: serial@200 {
     31		pinctrl-0 = <&usart0_pins>;
     32		pinctrl-names = "default";
     33		status = "okay";
     34	};
     35};
     36
     37&flx3 {
     38	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
     39	status = "okay";
     40
     41	spi3: spi@400 {
     42		pinctrl-0 = <&fc3_b_pins>;
     43		pinctrl-names = "default";
     44		status = "okay";
     45		cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
     46	};
     47};
     48
     49&gpio {
     50	fc3_b_pins: fc3-b-pins {
     51		/* SCK, MISO, MOSI */
     52		pins = "GPIO_51", "GPIO_52", "GPIO_53";
     53		function = "fc3_b";
     54	};
     55
     56	miim_c_pins: miim-c-pins {
     57		/* MDC, MDIO */
     58		pins = "GPIO_59", "GPIO_60";
     59		function = "miim_c";
     60	};
     61
     62	sgpio_a_pins: sgpio-a-pins {
     63		/* SCK, D0, D1 */
     64		pins = "GPIO_32", "GPIO_33", "GPIO_34";
     65		function = "sgpio_a";
     66	};
     67
     68	sgpio_b_pins: sgpio-b-pins {
     69		/* LD */
     70		pins = "GPIO_64";
     71		function = "sgpio_b";
     72	};
     73
     74	usart0_pins: usart0-pins {
     75		/* RXD, TXD */
     76		pins = "GPIO_25", "GPIO_26";
     77		function = "fc0_b";
     78	};
     79};
     80
     81&mdio0 {
     82	pinctrl-0 = <&miim_c_pins>;
     83	pinctrl-names = "default";
     84	reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
     85	clock-frequency = <2500000>;
     86	status = "okay";
     87
     88	phy4: ethernet-phy@5 {
     89		reg = <5>;
     90		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
     91	};
     92
     93	phy5: ethernet-phy@6 {
     94		reg = <6>;
     95		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
     96	};
     97
     98	phy6: ethernet-phy@7 {
     99		reg = <7>;
    100		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
    101	};
    102
    103	phy7: ethernet-phy@8 {
    104		reg = <8>;
    105		coma-mode-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
    106	};
    107};
    108
    109&mdio1 {
    110	status = "okay";
    111};
    112
    113&phy0 {
    114	status = "okay";
    115};
    116
    117&phy1 {
    118	status = "okay";
    119};
    120
    121&port0 {
    122	phys = <&serdes 0 CU(0)>;
    123	phy-handle = <&phy0>;
    124	phy-mode = "gmii";
    125	status = "okay";
    126};
    127
    128&port1 {
    129	phys = <&serdes 1 CU(1)>;
    130	phy-handle = <&phy1>;
    131	phy-mode = "gmii";
    132	status = "okay";
    133};
    134
    135&port4 {
    136	phys = <&serdes 4 SERDES6G(2)>;
    137	phy-handle = <&phy4>;
    138	phy-mode = "qsgmii";
    139	status = "okay";
    140};
    141
    142&port5 {
    143	phys = <&serdes 5 SERDES6G(2)>;
    144	phy-handle = <&phy5>;
    145	phy-mode = "qsgmii";
    146	status = "okay";
    147};
    148
    149&port6 {
    150	phys = <&serdes 6 SERDES6G(2)>;
    151	phy-handle = <&phy6>;
    152	phy-mode = "qsgmii";
    153	status = "okay";
    154};
    155
    156&port7 {
    157	phys = <&serdes 7 SERDES6G(2)>;
    158	phy-handle = <&phy7>;
    159	phy-mode = "qsgmii";
    160	status = "okay";
    161};
    162
    163&serdes {
    164	status = "okay";
    165};
    166
    167&sgpio {
    168	pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
    169	pinctrl-names = "default";
    170	bus-frequency = <8000000>;
    171	/* arbitrary range because all GPIOs are in software mode */
    172	microchip,sgpio-port-ranges = <0 11>;
    173	status = "okay";
    174
    175	sgpio_in: gpio@0 {
    176		ngpios = <128>;
    177	};
    178
    179	sgpio_out: gpio@1 {
    180		ngpios = <128>;
    181	};
    182};
    183
    184&switch {
    185	status = "okay";
    186};
    187
    188&watchdog {
    189	status = "okay";
    190};