cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lpc4350-hitex-eval.dts (8678B)


      1/*
      2 * Hitex LPC4350 Evaluation Board
      3 *
      4 * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
      5 *
      6 * This code is released using a dual license strategy: BSD/GPL
      7 * You can choose the licence that better fits your requirements.
      8 *
      9 * Released under the terms of 3-clause BSD License
     10 * Released under the terms of GNU General Public License Version 2.0
     11 *
     12 */
     13/dts-v1/;
     14
     15#include "lpc18xx.dtsi"
     16#include "lpc4350.dtsi"
     17
     18#include "dt-bindings/input/input.h"
     19#include "dt-bindings/gpio/gpio.h"
     20
     21/ {
     22	model = "Hitex LPC4350 Evaluation Board";
     23	compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
     24
     25	aliases {
     26		serial0 = &uart0;
     27		serial1 = &uart1;
     28		serial2 = &uart2;
     29		serial3 = &uart3;
     30	};
     31
     32	chosen {
     33		stdout-path = &uart0;
     34	};
     35
     36	memory@28000000 {
     37		device_type = "memory";
     38		reg = <0x28000000 0x800000>; /* 8 MB */
     39	};
     40
     41	pca_buttons {
     42		compatible = "gpio-keys-polled";
     43		poll-interval = <100>;
     44		autorepeat;
     45
     46		button0 {
     47			label = "joy:right";
     48			linux,code = <KEY_RIGHT>;
     49			gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
     50		};
     51
     52		button1 {
     53			label = "joy:up";
     54			linux,code = <KEY_UP>;
     55			gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
     56		};
     57
     58
     59		button2 {
     60			label = "joy:enter";
     61			linux,code = <KEY_ENTER>;
     62			gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
     63		};
     64
     65		button3 {
     66			label = "joy:left";
     67			linux,code = <KEY_LEFT>;
     68			gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
     69		};
     70
     71		button4 {
     72			label = "joy:down";
     73			linux,code = <KEY_DOWN>;
     74			gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
     75		};
     76
     77		button5 {
     78			label = "user:sw3";
     79			linux,code = <KEY_F1>;
     80			gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
     81		};
     82
     83		button6 {
     84			label = "user:sw4";
     85			linux,code = <KEY_F2>;
     86			gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
     87		};
     88
     89		button7 {
     90			label = "user:sw5";
     91			linux,code = <KEY_F3>;
     92			gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
     93		};
     94	};
     95
     96	pca_leds {
     97		compatible = "gpio-leds";
     98
     99		led0 {
    100			label = "ext:led0";
    101			gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
    102			linux,default-trigger = "heartbeat";
    103		};
    104
    105		led1 {
    106			label = "ext:led1";
    107			gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
    108		};
    109
    110		led2 {
    111			label = "ext:led2";
    112			gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
    113		};
    114
    115		led3 {
    116			label = "ext:led3";
    117			gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
    118		};
    119	};
    120
    121	vcc: vcc_fixed {
    122		compatible = "regulator-fixed";
    123		regulator-name = "3v3io";
    124		regulator-min-microvolt = <3300000>;
    125		regulator-max-microvolt = <3300000>;
    126	};
    127};
    128
    129&pinctrl {
    130	adc1_pins: adc1-pins {
    131		adc1_pins_cfg {
    132			pins = "pf_9";
    133			function = "adc";
    134			input-disable;
    135			bias-disable;
    136		};
    137	};
    138
    139	emc_pins: emc-pins {
    140		emc_addr0_23_cfg {
    141			pins =	"p2_9",  "p2_10", "p2_11", "p2_12",
    142				"p2_13", "p1_0",  "p1_1",  "p1_2",
    143				"p2_8",  "p2_7",  "p2_6",  "p2_2",
    144				"p2_1",  "p2_0",  "p6_8",  "p6_7",
    145				"pd_16", "pd_15", "pe_0",  "pe_1",
    146				"pe_2",  "pe_3",  "pe_4",  "pa_4";
    147			function = "emc";
    148			slew-rate = <1>;
    149			bias-disable;
    150			input-enable;
    151			input-schmitt-disable;
    152		};
    153
    154		emc_data0_15_cfg {
    155			pins =	"p1_7",  "p1_8",  "p1_9",  "p1_10",
    156				"p1_11", "p1_12", "p1_13", "p1_14",
    157				"p5_4",  "p5_5",  "p5_6",  "p5_7",
    158				"p5_0",  "p5_1",  "p5_2",  "p5_3";
    159			function = "emc";
    160			slew-rate = <1>;
    161			bias-disable;
    162			input-enable;
    163			input-schmitt-disable;
    164		};
    165
    166		emc_we_oe_cfg {
    167			pins = "p1_6", "p1_3";
    168			function = "emc";
    169			slew-rate = <1>;
    170			bias-disable;
    171			input-enable;
    172			input-schmitt-disable;
    173		};
    174
    175		emc_bls0_3_cfg {
    176			pins = "p1_4", "p6_6", "pd_13", "pd_10";
    177			function = "emc";
    178			slew-rate = <1>;
    179			bias-disable;
    180			input-enable;
    181			input-schmitt-disable;
    182		};
    183
    184		emc_cs0_cs2_cfg {
    185			pins = "p1_5", "pd_12";
    186			function = "emc";
    187			slew-rate = <1>;
    188			bias-disable;
    189			input-enable;
    190			input-schmitt-disable;
    191		};
    192
    193		emc_sdram_dqm0_3_cfg {
    194			pins = "p6_12", "p6_10", "pd_0", "pe_13";
    195			function = "emc";
    196			slew-rate = <1>;
    197			bias-disable;
    198			input-enable;
    199			input-schmitt-disable;
    200		};
    201
    202		emc_sdram_ras_cas_cfg {
    203			pins = "p6_5", "p6_4";
    204			function = "emc";
    205			slew-rate = <1>;
    206			bias-disable;
    207			input-enable;
    208			input-schmitt-disable;
    209		};
    210
    211		emc_sdram_dycs0_cfg {
    212			pins = "p6_9";
    213			function = "emc";
    214			slew-rate = <1>;
    215			bias-disable;
    216			input-enable;
    217			input-schmitt-disable;
    218		};
    219
    220		emc_sdram_cke_cfg {
    221			pins = "p6_11";
    222			function = "emc";
    223			slew-rate = <1>;
    224			bias-disable;
    225			input-enable;
    226			input-schmitt-disable;
    227		};
    228
    229		emc_sdram_clock_cfg {
    230			pins = "clk0", "clk1", "clk2", "clk3";
    231			function = "emc";
    232			slew-rate = <1>;
    233			bias-disable;
    234			input-enable;
    235			input-schmitt-disable;
    236		};
    237	};
    238
    239	enet_mii_pins: enet-mii-pins {
    240		enet_mii_rxd0_3_cfg {
    241			pins = "p1_15", "p0_0", "p9_3", "p9_2";
    242			function = "enet";
    243			bias-disable;
    244			input-enable;
    245		};
    246
    247		enet_mii_txd0_3_cfg {
    248			pins = "p1_18", "p1_20", "p9_4", "p9_5";
    249			function = "enet";
    250			bias-disable;
    251		};
    252
    253		enet_mii_crs_col_cfg {
    254			pins = "p9_0", "p9_6";
    255			function = "enet";
    256			bias-disable;
    257			input-enable;
    258		};
    259
    260		enet_mii_rx_clk_dv_er_cfg {
    261			pins = "pc_0", "p1_16", "p9_1";
    262			function = "enet";
    263			bias-disable;
    264			input-enable;
    265		};
    266
    267		enet_mii_tx_clk_en_cfg {
    268			pins = "p1_19", "p0_1";
    269			function = "enet";
    270			bias-disable;
    271			input-enable;
    272		};
    273
    274		enet_mdio_cfg {
    275			pins = "p1_17";
    276			function = "enet";
    277			bias-disable;
    278			input-enable;
    279		};
    280
    281		enet_mdc_cfg {
    282			pins = "pc_1";
    283			function = "enet";
    284			bias-disable;
    285		};
    286	};
    287
    288	i2c0_pins: i2c0-pins {
    289		i2c0_pins_cfg {
    290			pins = "i2c0_scl", "i2c0_sda";
    291			function = "i2c0";
    292			input-enable;
    293		};
    294	};
    295
    296	spifi_pins: spifi-pins {
    297		spifi_clk_cfg {
    298			pins = "p3_3";
    299			function = "spifi";
    300			slew-rate = <1>;
    301			bias-disable;
    302			input-enable;
    303			input-schmitt-disable;
    304		};
    305
    306		spifi_mosi_miso_sio2_3_cfg {
    307			pins = "p3_7", "p3_6", "p3_5", "p3_4";
    308			function = "spifi";
    309			slew-rate = <1>;
    310			bias-disable;
    311			input-enable;
    312			input-schmitt-disable;
    313		};
    314
    315		spifi_cs_cfg {
    316			pins = "p3_8";
    317			function = "spifi";
    318			slew-rate = <1>;
    319			bias-disable;
    320			input-enable;
    321			input-schmitt-disable;
    322		};
    323	};
    324
    325	uart0_pins: uart0-pins {
    326		uart0_rx_cfg {
    327			pins = "pf_11";
    328			function = "uart0";
    329			input-schmitt-disable;
    330			bias-disable;
    331			input-enable;
    332		};
    333
    334		uart0_tx_cfg {
    335			pins = "pf_10";
    336			function = "uart0";
    337			bias-pull-down;
    338		};
    339	};
    340};
    341
    342&adc1 {
    343	status = "okay";
    344	vref-supply = <&vcc>;
    345	pinctrl-names = "default";
    346	pinctrl-0 = <&adc1_pins>;
    347};
    348
    349&emc {
    350	status = "okay";
    351	pinctrl-names = "default";
    352	pinctrl-0 = <&emc_pins>;
    353
    354	cs0 {
    355		#address-cells = <2>;
    356		#size-cells = <1>;
    357		ranges;
    358
    359		mpmc,cs = <0>;
    360		mpmc,memory-width = <16>;
    361		mpmc,byte-lane-low;
    362		mpmc,write-enable-delay = <0>;
    363		mpmc,output-enable-delay = <0>;
    364		mpmc,read-access-delay = <70>;
    365		mpmc,page-mode-read-delay = <70>;
    366
    367		flash@0,0 {
    368			compatible = "sst,sst39vf320", "cfi-flash";
    369			reg = <0 0 0x400000>;
    370			bank-width = <2>;
    371			#address-cells = <1>;
    372			#size-cells = <1>;
    373
    374			partition@0 {
    375				label = "bootloader";
    376				reg = <0x000000 0x040000>; /* 256 KiB */
    377			};
    378
    379			partition@1 {
    380				label = "kernel";
    381				reg = <0x040000 0x2C0000>; /* 2.75 MiB */
    382			};
    383
    384			partition@2 {
    385				label = "rootfs";
    386				reg = <0x300000 0x100000>; /* 1 MiB */
    387			};
    388		};
    389	};
    390
    391	cs2 {
    392		#address-cells = <2>;
    393		#size-cells = <1>;
    394		ranges;
    395
    396		mpmc,cs = <2>;
    397		mpmc,memory-width = <16>;
    398		mpmc,byte-lane-low;
    399		mpmc,write-enable-delay = <0>;
    400		mpmc,output-enable-delay = <30>;
    401		mpmc,read-access-delay = <90>;
    402		mpmc,page-mode-read-delay = <55>;
    403		mpmc,write-access-delay = <55>;
    404		mpmc,turn-round-delay = <55>;
    405
    406		ext_sram: sram@2,0 {
    407			compatible = "mmio-sram";
    408			reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
    409		};
    410	};
    411};
    412
    413&enet_tx_clk {
    414	clock-frequency = <25000000>;
    415};
    416
    417&i2c0 {
    418	status = "okay";
    419	pinctrl-names = "default";
    420	pinctrl-0 = <&i2c0_pins>;
    421	clock-frequency = <400000>;
    422
    423	/* NXP SE97BTP with temperature sensor + eeprom */
    424	sensor@18 {
    425		compatible = "nxp,se97", "jedec,jc-42.4-temp";
    426		reg = <0x18>;
    427	};
    428
    429	eeprom@50 {
    430		compatible = "nxp,24c02", "atmel,24c02";
    431		reg = <0x50>;
    432	};
    433
    434	pca_gpio: gpio@24 {
    435		compatible = "nxp,pca9673";
    436		reg = <0x24>;
    437		gpio-controller;
    438		#gpio-cells = <2>;
    439	};
    440};
    441
    442&mac {
    443	status = "okay";
    444	phy-mode = "mii";
    445	pinctrl-names = "default";
    446	pinctrl-0 = <&enet_mii_pins>;
    447};
    448
    449&spifi {
    450	status = "okay";
    451	pinctrl-names = "default";
    452	pinctrl-0 = <&spifi_pins>;
    453
    454	flash {
    455		compatible = "jedec,spi-nor";
    456		spi-rx-bus-width = <4>;
    457		#address-cells = <1>;
    458		#size-cells = <1>;
    459
    460		partition@0 {
    461			label = "bootloader";
    462			reg = <0x000000 0x040000>; /* 256 KiB */
    463		};
    464
    465		partition@1 {
    466			label = "kernel";
    467			reg = <0x040000 0x2c0000>; /* 2.75 MiB */
    468		};
    469
    470		partition@2 {
    471			label = "rootfs";
    472			reg = <0x300000 0x500000>; /* 5 MiB */
    473		};
    474	};
    475};
    476
    477&uart0 {
    478	status = "okay";
    479	pinctrl-names = "default";
    480	pinctrl-0 = <&uart0_pins>;
    481};