cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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lpc4357-myd-lpc4357.dts (10485B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2/*
      3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
      4 *
      5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
      6 */
      7
      8/dts-v1/;
      9
     10#include "lpc18xx.dtsi"
     11#include "lpc4357.dtsi"
     12
     13#include <dt-bindings/gpio/gpio.h>
     14
     15/ {
     16	model = "MYIR Tech LPC4357 Development Board";
     17	compatible = "myir,myd-lpc4357", "nxp,lpc4357";
     18
     19	chosen {
     20		stdout-path = "serial3:115200n8";
     21	};
     22
     23	memory@28000000 {
     24		device_type = "memory";
     25		reg = <0x28000000 0x2000000>;
     26	};
     27
     28	leds {
     29		compatible = "gpio-leds";
     30		pinctrl-names = "default";
     31		pinctrl-0 = <&led_pins>;
     32
     33		led1 {
     34			gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
     35			default-state = "off";
     36		};
     37
     38		led2 {
     39			gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
     40			default-state = "off";
     41		};
     42
     43		led3 {
     44			gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
     45			default-state = "off";
     46		};
     47
     48		led4 {
     49			gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
     50			default-state = "off";
     51		};
     52
     53		led5 {
     54			gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
     55			default-state = "off";
     56		};
     57
     58		led6 {
     59			gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
     60			default-state = "off";
     61		};
     62	};
     63
     64	panel: panel {
     65		compatible = "innolux,at070tn92";
     66
     67		port {
     68			panel_input: endpoint {
     69				remote-endpoint = <&lcdc_output>;
     70			};
     71		};
     72	};
     73
     74	vcc: vcc_fixed {
     75		compatible = "regulator-fixed";
     76		regulator-name = "vcc-supply";
     77		regulator-min-microvolt = <3300000>;
     78		regulator-max-microvolt = <3300000>;
     79	};
     80
     81	vmmc: vmmc_fixed {
     82		compatible = "regulator-fixed";
     83		regulator-name = "vmmc-supply";
     84		regulator-min-microvolt = <3300000>;
     85		regulator-max-microvolt = <3300000>;
     86	};
     87};
     88
     89&pinctrl {
     90	can0_pins: can0-pins {
     91		can_rd_cfg {
     92			pins = "p3_1";
     93			function = "can0";
     94			input-enable;
     95		};
     96
     97		can_td_cfg {
     98			pins = "p3_2";
     99			function = "can0";
    100		};
    101	};
    102
    103	can1_pins: can1-pins {
    104		can_rd_cfg {
    105			pins = "pe_1";
    106			function = "can1";
    107			input-enable;
    108		};
    109
    110		can_td_cfg {
    111			pins = "pe_0";
    112			function = "can1";
    113		};
    114	};
    115
    116	emc_pins: emc-pins {
    117		emc_addr0_22_cfg {
    118			pins = "p2_9",  "p2_10", "p2_11", "p2_12",
    119			       "p2_13", "p1_0",  "p1_1",  "p1_2",
    120			       "p2_8",  "p2_7",  "p2_6",  "p2_2",
    121			       "p2_1",  "p2_0",  "p6_8",  "p6_7",
    122			       "pd_16", "pd_15", "pe_0",  "pe_1",
    123			       "pe_2",  "pe_3",  "pe_4";
    124			function = "emc";
    125			slew-rate = <1>;
    126			bias-disable;
    127		};
    128
    129		emc_data0_15_cfg {
    130			pins = "p1_7",  "p1_8",  "p1_9",  "p1_10",
    131			       "p1_11", "p1_12", "p1_13", "p1_14",
    132			       "p5_4",  "p5_5",  "p5_6",  "p5_7",
    133			       "p5_0",  "p5_1",  "p5_2",  "p5_3";
    134			function = "emc";
    135			input-enable;
    136			input-schmitt-disable;
    137			slew-rate = <1>;
    138			bias-disable;
    139		};
    140
    141		emc_we_oe_cfg {
    142			pins = "p1_6", "p1_3";
    143			function = "emc";
    144			slew-rate = <1>;
    145			bias-disable;
    146		};
    147
    148		emc_cs0_cfg {
    149			pins = "p1_5";
    150			function = "emc";
    151			slew-rate = <1>;
    152			bias-disable;
    153		};
    154
    155		emc_sdram_dqm0_1_cfg {
    156			pins = "p6_12", "p6_10";
    157			function = "emc";
    158			slew-rate = <1>;
    159			bias-disable;
    160		};
    161
    162		emc_sdram_ras_cas_cfg {
    163			pins = "p6_5", "p6_4";
    164			function = "emc";
    165			slew-rate = <1>;
    166			bias-disable;
    167		};
    168
    169		emc_sdram_dycs0_cfg {
    170			pins = "p6_9";
    171			function = "emc";
    172			slew-rate = <1>;
    173			bias-disable;
    174		};
    175
    176		emc_sdram_cke_cfg {
    177			pins = "p6_11";
    178			function = "emc";
    179			slew-rate = <1>;
    180			bias-disable;
    181		};
    182
    183		emc_sdram_clock_cfg {
    184			pins = "clk0";
    185			function = "emc";
    186			input-enable;
    187			input-schmitt-disable;
    188			slew-rate = <1>;
    189			bias-disable;
    190		};
    191	};
    192
    193	enet_rmii_pins: enet-rmii-pins {
    194		enet_rmii_rxd_cfg {
    195			pins = "p1_15", "p0_0";
    196			function = "enet";
    197			input-enable;
    198			input-schmitt-disable;
    199			slew-rate = <1>;
    200			bias-disable;
    201		};
    202
    203		enet_rmii_txd_cfg {
    204			pins = "p1_18", "p1_20";
    205			function = "enet";
    206			slew-rate = <1>;
    207			bias-disable;
    208		};
    209
    210		enet_rmii_rx_dv_cfg {
    211			pins = "p1_16";
    212			function = "enet";
    213			input-enable;
    214			input-schmitt-disable;
    215			bias-disable;
    216		};
    217
    218		enet_mdio_cfg {
    219			pins = "p1_17";
    220			function = "enet";
    221			input-enable;
    222			input-schmitt-disable;
    223			bias-disable;
    224		};
    225
    226		enet_mdc_cfg {
    227			pins = "pc_1";
    228			function = "enet";
    229			slew-rate = <1>;
    230			bias-disable;
    231		};
    232
    233		enet_rmii_tx_en_cfg {
    234			pins = "p0_1";
    235			function = "enet";
    236			bias-disable;
    237		};
    238
    239		enet_ref_clk_cfg {
    240			pins = "p1_19";
    241			function = "enet";
    242			slew-rate = <1>;
    243			input-enable;
    244			input-schmitt-disable;
    245			bias-disable;
    246		};
    247	};
    248
    249	i2c0_pins: i2c0-pins {
    250		i2c0_pins_cfg {
    251			pins = "i2c0_scl", "i2c0_sda";
    252			function = "i2c0";
    253			input-enable;
    254		};
    255	};
    256
    257	i2c1_pins: i2c1-pins {
    258		i2c1_pins_cfg {
    259			pins = "pe_15", "pe_13";
    260			function = "i2c1";
    261			input-enable;
    262		};
    263	};
    264
    265	lcd_pins: lcd-pins {
    266		lcd_vd0_23_cfg {
    267			pins = "p4_1", "p4_4", "p4_3",  "p4_2",
    268			       "p8_7", "p8_6", "p8_5",  "p8_4",
    269			       "p7_5", "p4_8", "p4_10", "p4_9",
    270			       "p8_3", "pb_6", "pb_5",  "pb_4",
    271			       "p7_4", "p7_3", "p7_2",  "p7_1",
    272			       "pb_3", "pb_2", "pb_1",  "pb_0";
    273			function = "lcd";
    274		};
    275
    276		lcd_vsync_en_dclk_lp_pwr_cfg {
    277			pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
    278			function = "lcd";
    279		};
    280	};
    281
    282	led_pins: led-pins {
    283		led_1_6_cfg {
    284			pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
    285			function = "gpio";
    286			bias-pull-down;
    287		};
    288	};
    289
    290	sdmmc_pins: sdmmc-pins {
    291		sdmmc_clk_cfg {
    292			pins = "pc_0";
    293			function = "sdmmc";
    294			slew-rate = <1>;
    295			bias-pull-down;
    296		};
    297
    298		sdmmc_cmd_dat0_3_cfg {
    299			pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
    300			function = "sdmmc";
    301			input-enable;
    302			input-schmitt-disable;
    303			slew-rate = <1>;
    304			bias-disable;
    305		};
    306
    307		sdmmc_cd_cfg {
    308			pins = "pc_8";
    309			function = "sdmmc";
    310			input-enable;
    311			bias-pull-down;
    312		};
    313	};
    314
    315	spifi_pins: spifi-pins {
    316		spifi_sck_cfg {
    317			pins = "p3_3";
    318			function = "spifi";
    319			input-enable;
    320			input-schmitt-disable;
    321			slew-rate = <1>;
    322			bias-disable;
    323		};
    324
    325		spifi_mosi_miso_sio2_sio3_cfg {
    326			pins = "p3_7", "p3_6", "p3_5", "p3_4";
    327			function = "spifi";
    328			input-enable;
    329			input-schmitt-disable;
    330			slew-rate = <1>;
    331			bias-disable;
    332		};
    333
    334		spifi_cs_cfg {
    335			pins = "p3_8";
    336			function = "spifi";
    337			bias-disable;
    338		};
    339	};
    340
    341	ssp1_pins: ssp1-pins {
    342		ssp1_sck_cfg {
    343			pins = "pf_4";
    344			function = "ssp1";
    345			slew-rate = <1>;
    346			bias-pull-down;
    347		};
    348
    349		ssp1_miso_cfg {
    350			pins = "pf_6";
    351			function = "ssp1";
    352			input-enable;
    353			input-schmitt-disable;
    354			slew-rate = <1>;
    355			bias-pull-down;
    356		};
    357
    358		ssp1_mosi_cfg {
    359			pins = "pf_7";
    360			function = "ssp1";
    361			slew-rate = <1>;
    362			bias-pull-down;
    363		};
    364
    365		ssp1_ssel_cfg {
    366			pins = "pf_5";
    367			function = "gpio";
    368			bias-disable;
    369		};
    370	};
    371
    372	uart0_pins: uart0-pins {
    373		uart0_rxd_cfg {
    374			pins = "pf_11";
    375			function = "uart0";
    376			input-enable;
    377			input-schmitt-disable;
    378			bias-disable;
    379		};
    380
    381		uart0_clk_dir_txd_cfg {
    382			pins = "pf_8", "pf_9", "pf_10";
    383			function = "uart0";
    384			bias-pull-down;
    385		};
    386	};
    387
    388	uart1_pins: uart1-pins {
    389		uart1_rxd_cfg {
    390			pins = "pc_14";
    391			function = "uart1";
    392			bias-disable;
    393			input-enable;
    394			input-schmitt-disable;
    395		};
    396
    397		uart1_dtr_txd_cfg {
    398			pins = "pc_12", "pc_13";
    399			function = "uart1";
    400			bias-pull-down;
    401		};
    402	};
    403
    404	uart2_pins: uart2-pins {
    405		uart2_rxd_cfg {
    406			pins = "pa_2";
    407			function = "uart2";
    408			bias-disable;
    409			input-enable;
    410			input-schmitt-disable;
    411		};
    412
    413		uart2_txd_cfg {
    414			pins = "pa_1";
    415			function = "uart2";
    416			bias-pull-down;
    417		};
    418	};
    419
    420	uart3_pins: uart3-pins {
    421		uart3_rx_cfg {
    422			pins = "p2_4";
    423			function = "uart3";
    424			bias-disable;
    425			input-enable;
    426			input-schmitt-disable;
    427		};
    428
    429		uart3_tx_cfg {
    430			pins = "p2_3";
    431			function = "uart3";
    432			bias-pull-down;
    433		};
    434	};
    435
    436	usb0_pins: usb0-pins {
    437		usb0_pwr_enable_cfg {
    438			pins = "p6_3";
    439			function = "usb0";
    440		};
    441
    442		usb0_pwr_fault_cfg {
    443			pins = "p8_0";
    444			function = "usb0";
    445			bias-disable;
    446			input-enable;
    447		};
    448	};
    449};
    450
    451&adc1 {
    452	status = "okay";
    453	vref-supply = <&vcc>;
    454};
    455
    456&can0 {
    457	status = "okay";
    458	pinctrl-names = "default";
    459	pinctrl-0 = <&can0_pins>;
    460};
    461
    462/* Pin conflict with EMC, muxed by JP5 and JP6 */
    463&can1 {
    464	status = "disabled";
    465	pinctrl-names = "default";
    466	pinctrl-0 = <&can1_pins>;
    467};
    468
    469&emc {
    470	status = "okay";
    471	pinctrl-names = "default";
    472	pinctrl-0 = <&emc_pins>;
    473
    474	cs0 {
    475		#address-cells = <2>;
    476		#size-cells = <1>;
    477		ranges;
    478
    479		mpmc,cs = <0>;
    480		mpmc,memory-width = <16>;
    481		mpmc,byte-lane-low;
    482		mpmc,write-enable-delay = <0>;
    483		mpmc,output-enable-delay = <0>;
    484		mpmc,read-access-delay = <70>;
    485		mpmc,page-mode-read-delay = <70>;
    486
    487		/* SST/Microchip SST39VF1601 */
    488		flash@0,0 {
    489			compatible = "cfi-flash";
    490			reg = <0 0 0x400000>;
    491			bank-width = <2>;
    492		};
    493	};
    494};
    495
    496&enet_tx_clk {
    497	clock-frequency = <50000000>;
    498};
    499
    500&i2c0 {
    501	status = "okay";
    502	pinctrl-names = "default";
    503	pinctrl-0 = <&i2c0_pins>;
    504	clock-frequency = <400000>;
    505};
    506
    507&i2c1 {
    508	status = "okay";
    509	pinctrl-names = "default";
    510	pinctrl-0 = <&i2c1_pins>;
    511	clock-frequency = <400000>;
    512
    513	sensor@49 {
    514		compatible = "lm75";
    515		reg = <0x49>;
    516	};
    517
    518	eeprom@50 {
    519		compatible = "atmel,24c512";
    520		reg = <0x50>;
    521	};
    522};
    523
    524&lcdc {
    525	status = "okay";
    526	pinctrl-names = "default";
    527	pinctrl-0 = <&lcd_pins>;
    528
    529	max-memory-bandwidth = <92240000>;
    530
    531	port {
    532		lcdc_output: endpoint {
    533			remote-endpoint = <&panel_input>;
    534			arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
    535		};
    536	};
    537};
    538
    539&mac {
    540	status = "okay";
    541	phy-mode = "rmii";
    542	pinctrl-names = "default";
    543	pinctrl-0 = <&enet_rmii_pins>;
    544	phy-handle = <&phy1>;
    545
    546	mdio0 {
    547		#address-cells = <1>;
    548		#size-cells = <0>;
    549		compatible = "snps,dwmac-mdio";
    550
    551		phy1: ethernet-phy@1 {
    552			reg = <1>;
    553		};
    554	};
    555};
    556
    557&mmcsd {
    558	status = "okay";
    559	pinctrl-names = "default";
    560	pinctrl-0 = <&sdmmc_pins>;
    561	bus-width = <4>;
    562	vmmc-supply = <&vmmc>;
    563};
    564
    565/* Pin conflict with SSP0, the latter is routed to J17 pin header */
    566&spifi {
    567	status = "okay";
    568	pinctrl-names = "default";
    569	pinctrl-0 = <&spifi_pins>;
    570
    571	/* Atmel AT25DF321A */
    572	flash {
    573		compatible = "jedec,spi-nor";
    574		spi-max-frequency = <51000000>;
    575		spi-cpol;
    576		spi-cpha;
    577	};
    578};
    579
    580&ssp1 {
    581	status = "okay";
    582	pinctrl-names = "default";
    583	pinctrl-0 = <&ssp1_pins>;
    584	num-cs = <1>;
    585	cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
    586};
    587
    588/* Routed to J17 pin header */
    589&uart0 {
    590	status = "okay";
    591	pinctrl-names = "default";
    592	pinctrl-0 = <&uart0_pins>;
    593};
    594
    595/* RS485 */
    596&uart1 {
    597	status = "okay";
    598	pinctrl-names = "default";
    599	pinctrl-0 = <&uart1_pins>;
    600};
    601
    602/* Routed to J17 pin header */
    603&uart2 {
    604	status = "okay";
    605	pinctrl-names = "default";
    606	pinctrl-0 = <&uart2_pins>;
    607};
    608
    609&uart3 {
    610	status = "okay";
    611	pinctrl-names = "default";
    612	pinctrl-0 = <&uart3_pins>;
    613};
    614
    615&usb0 {
    616	status = "okay";
    617	pinctrl-names = "default";
    618	pinctrl-0 = <&usb0_pins>;
    619};