ls1021a.dtsi (25972B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/thermal/thermal.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 interrupt-parent = <&gic>; 13 14 aliases { 15 crypto = &crypto; 16 ethernet0 = &enet0; 17 ethernet1 = &enet1; 18 ethernet2 = &enet2; 19 rtc1 = &ftm_alarm0; 20 serial0 = &lpuart0; 21 serial1 = &lpuart1; 22 serial2 = &lpuart2; 23 serial3 = &lpuart3; 24 serial4 = &lpuart4; 25 serial5 = &lpuart5; 26 sysclk = &sysclk; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@f00 { 34 compatible = "arm,cortex-a7"; 35 device_type = "cpu"; 36 reg = <0xf00>; 37 clocks = <&clockgen 1 0>; 38 #cooling-cells = <2>; 39 }; 40 41 cpu1: cpu@f01 { 42 compatible = "arm,cortex-a7"; 43 device_type = "cpu"; 44 reg = <0xf01>; 45 clocks = <&clockgen 1 0>; 46 #cooling-cells = <2>; 47 }; 48 }; 49 50 memory@0 { 51 device_type = "memory"; 52 reg = <0x0 0x0 0x0 0x0>; 53 }; 54 55 sysclk: sysclk { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <100000000>; 59 clock-output-names = "sysclk"; 60 }; 61 62 timer { 63 compatible = "arm,armv7-timer"; 64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a7-pmu"; 72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 74 interrupt-affinity = <&cpu0>, <&cpu1>; 75 }; 76 77 reboot { 78 compatible = "syscon-reboot"; 79 regmap = <&dcfg>; 80 offset = <0xb0>; 81 mask = <0x02>; 82 }; 83 84 soc { 85 compatible = "simple-bus"; 86 #address-cells = <2>; 87 #size-cells = <2>; 88 device_type = "soc"; 89 interrupt-parent = <&gic>; 90 ranges; 91 92 ddr: memory-controller@1080000 { 93 compatible = "fsl,qoriq-memory-controller"; 94 reg = <0x0 0x1080000 0x0 0x1000>; 95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 96 big-endian; 97 }; 98 99 gic: interrupt-controller@1400000 { 100 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 101 #interrupt-cells = <3>; 102 interrupt-controller; 103 reg = <0x0 0x1401000 0x0 0x1000>, 104 <0x0 0x1402000 0x0 0x2000>, 105 <0x0 0x1404000 0x0 0x2000>, 106 <0x0 0x1406000 0x0 0x2000>; 107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 108 109 }; 110 111 msi1: msi-controller@1570e00 { 112 compatible = "fsl,ls1021a-msi"; 113 reg = <0x0 0x1570e00 0x0 0x8>; 114 msi-controller; 115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 msi2: msi-controller@1570e08 { 119 compatible = "fsl,ls1021a-msi"; 120 reg = <0x0 0x1570e08 0x0 0x8>; 121 msi-controller; 122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 123 }; 124 125 ifc: memory-controller@1530000 { 126 compatible = "fsl,ifc"; 127 reg = <0x0 0x1530000 0x0 0x10000>; 128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 129 status = "disabled"; 130 }; 131 132 dcfg: dcfg@1ee0000 { 133 compatible = "fsl,ls1021a-dcfg", "syscon"; 134 reg = <0x0 0x1ee0000 0x0 0x1000>; 135 big-endian; 136 }; 137 138 qspi: spi@1550000 { 139 compatible = "fsl,ls1021a-qspi"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 reg = <0x0 0x1550000 0x0 0x10000>, 143 <0x0 0x40000000 0x0 0x20000000>; 144 reg-names = "QuadSPI", "QuadSPI-memory"; 145 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 146 clock-names = "qspi_en", "qspi"; 147 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 148 status = "disabled"; 149 }; 150 151 esdhc: esdhc@1560000 { 152 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 153 reg = <0x0 0x1560000 0x0 0x10000>; 154 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 155 clock-frequency = <0>; 156 voltage-ranges = <1800 1800 3300 3300>; 157 sdhci,auto-cmd12; 158 big-endian; 159 bus-width = <4>; 160 status = "disabled"; 161 }; 162 163 sata: sata@3200000 { 164 compatible = "fsl,ls1021a-ahci"; 165 reg = <0x0 0x3200000 0x0 0x10000>, 166 <0x0 0x20220520 0x0 0x4>; 167 reg-names = "ahci", "sata-ecc"; 168 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&clockgen 4 1>; 170 dma-coherent; 171 status = "disabled"; 172 }; 173 174 scfg: scfg@1570000 { 175 compatible = "fsl,ls1021a-scfg", "syscon"; 176 reg = <0x0 0x1570000 0x0 0x10000>; 177 big-endian; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0x0 0x0 0x1570000 0x10000>; 181 182 extirq: interrupt-controller@1ac { 183 compatible = "fsl,ls1021a-extirq"; 184 #interrupt-cells = <2>; 185 #address-cells = <0>; 186 interrupt-controller; 187 reg = <0x1ac 4>; 188 interrupt-map = 189 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 190 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 191 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 192 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 193 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 194 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-map-mask = <0x7 0x0>; 196 }; 197 }; 198 199 crypto: crypto@1700000 { 200 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 201 fsl,sec-era = <7>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0x0 0x1700000 0x0 0x100000>; 205 ranges = <0x0 0x0 0x1700000 0x100000>; 206 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 207 dma-coherent; 208 209 sec_jr0: jr@10000 { 210 compatible = "fsl,sec-v5.0-job-ring", 211 "fsl,sec-v4.0-job-ring"; 212 reg = <0x10000 0x10000>; 213 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 sec_jr1: jr@20000 { 217 compatible = "fsl,sec-v5.0-job-ring", 218 "fsl,sec-v4.0-job-ring"; 219 reg = <0x20000 0x10000>; 220 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 sec_jr2: jr@30000 { 224 compatible = "fsl,sec-v5.0-job-ring", 225 "fsl,sec-v4.0-job-ring"; 226 reg = <0x30000 0x10000>; 227 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 228 }; 229 230 sec_jr3: jr@40000 { 231 compatible = "fsl,sec-v5.0-job-ring", 232 "fsl,sec-v4.0-job-ring"; 233 reg = <0x40000 0x10000>; 234 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 235 }; 236 237 }; 238 239 clockgen: clocking@1ee1000 { 240 compatible = "fsl,ls1021a-clockgen"; 241 reg = <0x0 0x1ee1000 0x0 0x1000>; 242 #clock-cells = <2>; 243 clocks = <&sysclk>; 244 }; 245 246 tmu: tmu@1f00000 { 247 compatible = "fsl,qoriq-tmu"; 248 reg = <0x0 0x1f00000 0x0 0x10000>; 249 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 250 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; 251 fsl,tmu-calibration = <0x00000000 0x00000020>, 252 <0x00000001 0x00000024>, 253 <0x00000002 0x0000002a>, 254 <0x00000003 0x00000032>, 255 <0x00000004 0x00000038>, 256 <0x00000005 0x0000003e>, 257 <0x00000006 0x00000043>, 258 <0x00000007 0x0000004a>, 259 <0x00000008 0x00000050>, 260 <0x00000009 0x00000059>, 261 <0x0000000a 0x0000005f>, 262 <0x0000000b 0x00000066>, 263 264 <0x00010000 0x00000023>, 265 <0x00010001 0x0000002b>, 266 <0x00010002 0x00000033>, 267 <0x00010003 0x0000003a>, 268 <0x00010004 0x00000042>, 269 <0x00010005 0x0000004a>, 270 <0x00010006 0x00000054>, 271 <0x00010007 0x0000005c>, 272 <0x00010008 0x00000065>, 273 <0x00010009 0x0000006f>, 274 275 <0x00020000 0x00000029>, 276 <0x00020001 0x00000033>, 277 <0x00020002 0x0000003d>, 278 <0x00020003 0x00000048>, 279 <0x00020004 0x00000054>, 280 <0x00020005 0x00000060>, 281 <0x00020006 0x0000006c>, 282 283 <0x00030000 0x00000025>, 284 <0x00030001 0x00000033>, 285 <0x00030002 0x00000043>, 286 <0x00030003 0x00000055>; 287 #thermal-sensor-cells = <1>; 288 }; 289 290 dspi0: spi@2100000 { 291 compatible = "fsl,ls1021a-v1.0-dspi"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x0 0x2100000 0x0 0x10000>; 295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 296 clock-names = "dspi"; 297 clocks = <&clockgen 4 1>; 298 spi-num-chipselects = <6>; 299 big-endian; 300 status = "disabled"; 301 }; 302 303 dspi1: spi@2110000 { 304 compatible = "fsl,ls1021a-v1.0-dspi"; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 reg = <0x0 0x2110000 0x0 0x10000>; 308 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 309 clock-names = "dspi"; 310 clocks = <&clockgen 4 1>; 311 spi-num-chipselects = <6>; 312 big-endian; 313 status = "disabled"; 314 }; 315 316 i2c0: i2c@2180000 { 317 compatible = "fsl,vf610-i2c"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x0 0x2180000 0x0 0x10000>; 321 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clockgen 4 1>; 323 dma-names = "rx", "tx"; 324 dmas = <&edma0 1 38>, <&edma0 1 39>; 325 status = "disabled"; 326 }; 327 328 i2c1: i2c@2190000 { 329 compatible = "fsl,vf610-i2c"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0x0 0x2190000 0x0 0x10000>; 333 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clockgen 4 1>; 335 dma-names = "rx", "tx"; 336 dmas = <&edma0 1 36>, <&edma0 1 37>; 337 status = "disabled"; 338 }; 339 340 i2c2: i2c@21a0000 { 341 compatible = "fsl,vf610-i2c"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 reg = <0x0 0x21a0000 0x0 0x10000>; 345 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clockgen 4 1>; 347 dma-names = "rx", "tx"; 348 dmas = <&edma0 1 34>, <&edma0 1 35>; 349 status = "disabled"; 350 }; 351 352 uart0: serial@21c0500 { 353 compatible = "fsl,16550-FIFO64", "ns16550a"; 354 reg = <0x0 0x21c0500 0x0 0x100>; 355 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 356 clock-frequency = <0>; 357 fifo-size = <15>; 358 status = "disabled"; 359 }; 360 361 uart1: serial@21c0600 { 362 compatible = "fsl,16550-FIFO64", "ns16550a"; 363 reg = <0x0 0x21c0600 0x0 0x100>; 364 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 365 clock-frequency = <0>; 366 fifo-size = <15>; 367 status = "disabled"; 368 }; 369 370 uart2: serial@21d0500 { 371 compatible = "fsl,16550-FIFO64", "ns16550a"; 372 reg = <0x0 0x21d0500 0x0 0x100>; 373 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 374 clock-frequency = <0>; 375 fifo-size = <15>; 376 status = "disabled"; 377 }; 378 379 uart3: serial@21d0600 { 380 compatible = "fsl,16550-FIFO64", "ns16550a"; 381 reg = <0x0 0x21d0600 0x0 0x100>; 382 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 383 clock-frequency = <0>; 384 fifo-size = <15>; 385 status = "disabled"; 386 }; 387 388 counter0: counter@29d0000 { 389 compatible = "fsl,ftm-quaddec"; 390 reg = <0x0 0x29d0000 0x0 0x10000>; 391 big-endian; 392 status = "disabled"; 393 }; 394 395 counter1: counter@29e0000 { 396 compatible = "fsl,ftm-quaddec"; 397 reg = <0x0 0x29e0000 0x0 0x10000>; 398 big-endian; 399 status = "disabled"; 400 }; 401 402 counter2: counter@29f0000 { 403 compatible = "fsl,ftm-quaddec"; 404 reg = <0x0 0x29f0000 0x0 0x10000>; 405 big-endian; 406 status = "disabled"; 407 }; 408 409 counter3: counter@2a00000 { 410 compatible = "fsl,ftm-quaddec"; 411 reg = <0x0 0x2a00000 0x0 0x10000>; 412 big-endian; 413 status = "disabled"; 414 }; 415 416 gpio0: gpio@2300000 { 417 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 418 reg = <0x0 0x2300000 0x0 0x10000>; 419 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 426 gpio1: gpio@2310000 { 427 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 428 reg = <0x0 0x2310000 0x0 0x10000>; 429 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 436 gpio2: gpio@2320000 { 437 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 438 reg = <0x0 0x2320000 0x0 0x10000>; 439 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 446 gpio3: gpio@2330000 { 447 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 448 reg = <0x0 0x2330000 0x0 0x10000>; 449 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 }; 455 456 lpuart0: serial@2950000 { 457 compatible = "fsl,ls1021a-lpuart"; 458 reg = <0x0 0x2950000 0x0 0x1000>; 459 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&sysclk>; 461 clock-names = "ipg"; 462 status = "disabled"; 463 }; 464 465 lpuart1: serial@2960000 { 466 compatible = "fsl,ls1021a-lpuart"; 467 reg = <0x0 0x2960000 0x0 0x1000>; 468 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clockgen 4 1>; 470 clock-names = "ipg"; 471 status = "disabled"; 472 }; 473 474 lpuart2: serial@2970000 { 475 compatible = "fsl,ls1021a-lpuart"; 476 reg = <0x0 0x2970000 0x0 0x1000>; 477 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clockgen 4 1>; 479 clock-names = "ipg"; 480 status = "disabled"; 481 }; 482 483 lpuart3: serial@2980000 { 484 compatible = "fsl,ls1021a-lpuart"; 485 reg = <0x0 0x2980000 0x0 0x1000>; 486 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&clockgen 4 1>; 488 clock-names = "ipg"; 489 status = "disabled"; 490 }; 491 492 lpuart4: serial@2990000 { 493 compatible = "fsl,ls1021a-lpuart"; 494 reg = <0x0 0x2990000 0x0 0x1000>; 495 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clockgen 4 1>; 497 clock-names = "ipg"; 498 status = "disabled"; 499 }; 500 501 lpuart5: serial@29a0000 { 502 compatible = "fsl,ls1021a-lpuart"; 503 reg = <0x0 0x29a0000 0x0 0x1000>; 504 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clockgen 4 1>; 506 clock-names = "ipg"; 507 status = "disabled"; 508 }; 509 510 pwm0: pwm@29d0000 { 511 compatible = "fsl,vf610-ftm-pwm"; 512 #pwm-cells = <3>; 513 reg = <0x0 0x29d0000 0x0 0x10000>; 514 clock-names = "ftm_sys", "ftm_ext", 515 "ftm_fix", "ftm_cnt_clk_en"; 516 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 517 <&clockgen 4 1>, <&clockgen 4 1>; 518 big-endian; 519 status = "disabled"; 520 }; 521 522 pwm1: pwm@29e0000 { 523 compatible = "fsl,vf610-ftm-pwm"; 524 #pwm-cells = <3>; 525 reg = <0x0 0x29e0000 0x0 0x10000>; 526 clock-names = "ftm_sys", "ftm_ext", 527 "ftm_fix", "ftm_cnt_clk_en"; 528 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 529 <&clockgen 4 1>, <&clockgen 4 1>; 530 big-endian; 531 status = "disabled"; 532 }; 533 534 pwm2: pwm@29f0000 { 535 compatible = "fsl,vf610-ftm-pwm"; 536 #pwm-cells = <3>; 537 reg = <0x0 0x29f0000 0x0 0x10000>; 538 clock-names = "ftm_sys", "ftm_ext", 539 "ftm_fix", "ftm_cnt_clk_en"; 540 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 541 <&clockgen 4 1>, <&clockgen 4 1>; 542 big-endian; 543 status = "disabled"; 544 }; 545 546 pwm3: pwm@2a00000 { 547 compatible = "fsl,vf610-ftm-pwm"; 548 #pwm-cells = <3>; 549 reg = <0x0 0x2a00000 0x0 0x10000>; 550 clock-names = "ftm_sys", "ftm_ext", 551 "ftm_fix", "ftm_cnt_clk_en"; 552 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 553 <&clockgen 4 1>, <&clockgen 4 1>; 554 big-endian; 555 status = "disabled"; 556 }; 557 558 pwm4: pwm@2a10000 { 559 compatible = "fsl,vf610-ftm-pwm"; 560 #pwm-cells = <3>; 561 reg = <0x0 0x2a10000 0x0 0x10000>; 562 clock-names = "ftm_sys", "ftm_ext", 563 "ftm_fix", "ftm_cnt_clk_en"; 564 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 565 <&clockgen 4 1>, <&clockgen 4 1>; 566 big-endian; 567 status = "disabled"; 568 }; 569 570 pwm5: pwm@2a20000 { 571 compatible = "fsl,vf610-ftm-pwm"; 572 #pwm-cells = <3>; 573 reg = <0x0 0x2a20000 0x0 0x10000>; 574 clock-names = "ftm_sys", "ftm_ext", 575 "ftm_fix", "ftm_cnt_clk_en"; 576 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 577 <&clockgen 4 1>, <&clockgen 4 1>; 578 big-endian; 579 status = "disabled"; 580 }; 581 582 pwm6: pwm@2a30000 { 583 compatible = "fsl,vf610-ftm-pwm"; 584 #pwm-cells = <3>; 585 reg = <0x0 0x2a30000 0x0 0x10000>; 586 clock-names = "ftm_sys", "ftm_ext", 587 "ftm_fix", "ftm_cnt_clk_en"; 588 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 589 <&clockgen 4 1>, <&clockgen 4 1>; 590 big-endian; 591 status = "disabled"; 592 }; 593 594 pwm7: pwm@2a40000 { 595 compatible = "fsl,vf610-ftm-pwm"; 596 #pwm-cells = <3>; 597 reg = <0x0 0x2a40000 0x0 0x10000>; 598 clock-names = "ftm_sys", "ftm_ext", 599 "ftm_fix", "ftm_cnt_clk_en"; 600 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 601 <&clockgen 4 1>, <&clockgen 4 1>; 602 big-endian; 603 status = "disabled"; 604 }; 605 606 wdog0: watchdog@2ad0000 { 607 compatible = "fsl,imx21-wdt"; 608 reg = <0x0 0x2ad0000 0x0 0x10000>; 609 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clockgen 4 1>; 611 clock-names = "wdog-en"; 612 big-endian; 613 }; 614 615 sai1: sai@2b50000 { 616 #sound-dai-cells = <0>; 617 compatible = "fsl,vf610-sai"; 618 reg = <0x0 0x2b50000 0x0 0x10000>; 619 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 621 <&clockgen 4 1>, <&clockgen 4 1>; 622 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 623 dma-names = "tx", "rx"; 624 dmas = <&edma0 1 47>, 625 <&edma0 1 46>; 626 status = "disabled"; 627 }; 628 629 sai2: sai@2b60000 { 630 #sound-dai-cells = <0>; 631 compatible = "fsl,vf610-sai"; 632 reg = <0x0 0x2b60000 0x0 0x10000>; 633 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 635 <&clockgen 4 1>, <&clockgen 4 1>; 636 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 637 dma-names = "tx", "rx"; 638 dmas = <&edma0 1 45>, 639 <&edma0 1 44>; 640 status = "disabled"; 641 }; 642 643 edma0: edma@2c00000 { 644 #dma-cells = <2>; 645 compatible = "fsl,vf610-edma"; 646 reg = <0x0 0x2c00000 0x0 0x10000>, 647 <0x0 0x2c10000 0x0 0x10000>, 648 <0x0 0x2c20000 0x0 0x10000>; 649 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "edma-tx", "edma-err"; 652 dma-channels = <32>; 653 big-endian; 654 clock-names = "dmamux0", "dmamux1"; 655 clocks = <&clockgen 4 1>, 656 <&clockgen 4 1>; 657 }; 658 659 dcu: dcu@2ce0000 { 660 compatible = "fsl,ls1021a-dcu"; 661 reg = <0x0 0x2ce0000 0x0 0x10000>; 662 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&clockgen 4 0>, 664 <&clockgen 4 0>; 665 clock-names = "dcu", "pix"; 666 big-endian; 667 status = "disabled"; 668 }; 669 670 mdio0: mdio@2d24000 { 671 compatible = "gianfar"; 672 device_type = "mdio"; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 reg = <0x0 0x2d24000 0x0 0x4000>, 676 <0x0 0x2d10030 0x0 0x4>; 677 }; 678 679 mdio1: mdio@2d64000 { 680 compatible = "gianfar"; 681 device_type = "mdio"; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 reg = <0x0 0x2d64000 0x0 0x4000>, 685 <0x0 0x2d50030 0x0 0x4>; 686 }; 687 688 ptp_clock@2d10e00 { 689 compatible = "fsl,etsec-ptp"; 690 reg = <0x0 0x2d10e00 0x0 0xb0>; 691 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 692 fsl,tclk-period = <5>; 693 fsl,tmr-prsc = <2>; 694 fsl,tmr-add = <0xaaaaaaab>; 695 fsl,tmr-fiper1 = <999999995>; 696 fsl,tmr-fiper2 = <999999995>; 697 fsl,max-adj = <499999999>; 698 fsl,extts-fifo; 699 }; 700 701 enet0: ethernet@2d10000 { 702 compatible = "fsl,etsec2"; 703 device_type = "network"; 704 #address-cells = <2>; 705 #size-cells = <2>; 706 interrupt-parent = <&gic>; 707 model = "eTSEC"; 708 fsl,magic-packet; 709 ranges; 710 dma-coherent; 711 712 queue-group@2d10000 { 713 #address-cells = <2>; 714 #size-cells = <2>; 715 reg = <0x0 0x2d10000 0x0 0x1000>; 716 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 719 }; 720 721 queue-group@2d14000 { 722 #address-cells = <2>; 723 #size-cells = <2>; 724 reg = <0x0 0x2d14000 0x0 0x1000>; 725 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 728 }; 729 }; 730 731 enet1: ethernet@2d50000 { 732 compatible = "fsl,etsec2"; 733 device_type = "network"; 734 #address-cells = <2>; 735 #size-cells = <2>; 736 interrupt-parent = <&gic>; 737 model = "eTSEC"; 738 ranges; 739 dma-coherent; 740 741 queue-group@2d50000 { 742 #address-cells = <2>; 743 #size-cells = <2>; 744 reg = <0x0 0x2d50000 0x0 0x1000>; 745 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 queue-group@2d54000 { 751 #address-cells = <2>; 752 #size-cells = <2>; 753 reg = <0x0 0x2d54000 0x0 0x1000>; 754 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 757 }; 758 }; 759 760 enet2: ethernet@2d90000 { 761 compatible = "fsl,etsec2"; 762 device_type = "network"; 763 #address-cells = <2>; 764 #size-cells = <2>; 765 interrupt-parent = <&gic>; 766 model = "eTSEC"; 767 ranges; 768 dma-coherent; 769 770 queue-group@2d90000 { 771 #address-cells = <2>; 772 #size-cells = <2>; 773 reg = <0x0 0x2d90000 0x0 0x1000>; 774 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 777 }; 778 779 queue-group@2d94000 { 780 #address-cells = <2>; 781 #size-cells = <2>; 782 reg = <0x0 0x2d94000 0x0 0x1000>; 783 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 786 }; 787 }; 788 789 usb2: usb@8600000 { 790 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 791 reg = <0x0 0x8600000 0x0 0x1000>; 792 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 793 dr_mode = "host"; 794 phy_type = "ulpi"; 795 }; 796 797 usb3: usb@3100000 { 798 compatible = "snps,dwc3"; 799 reg = <0x0 0x3100000 0x0 0x10000>; 800 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 801 dr_mode = "host"; 802 snps,quirk-frame-length-adjustment = <0x20>; 803 snps,dis_rxdet_inp3_quirk; 804 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 805 }; 806 807 pcie@3400000 { 808 compatible = "fsl,ls1021a-pcie"; 809 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ 810 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 811 reg-names = "regs", "config"; 812 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 813 fsl,pcie-scfg = <&scfg 0>; 814 #address-cells = <3>; 815 #size-cells = <2>; 816 device_type = "pci"; 817 num-viewport = <6>; 818 bus-range = <0x0 0xff>; 819 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ 820 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 821 msi-parent = <&msi1>, <&msi2>; 822 #interrupt-cells = <1>; 823 interrupt-map-mask = <0 0 0 7>; 824 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 825 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 826 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 827 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 828 status = "disabled"; 829 }; 830 831 pcie@3500000 { 832 compatible = "fsl,ls1021a-pcie"; 833 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ 834 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 835 reg-names = "regs", "config"; 836 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 837 fsl,pcie-scfg = <&scfg 1>; 838 #address-cells = <3>; 839 #size-cells = <2>; 840 device_type = "pci"; 841 num-viewport = <6>; 842 bus-range = <0x0 0xff>; 843 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ 844 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 845 msi-parent = <&msi1>, <&msi2>; 846 #interrupt-cells = <1>; 847 interrupt-map-mask = <0 0 0 7>; 848 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 849 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 850 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 851 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 852 status = "disabled"; 853 }; 854 855 can0: can@2a70000 { 856 compatible = "fsl,ls1021ar2-flexcan"; 857 reg = <0x0 0x2a70000 0x0 0x1000>; 858 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 860 clock-names = "ipg", "per"; 861 big-endian; 862 }; 863 864 can1: can@2a80000 { 865 compatible = "fsl,ls1021ar2-flexcan"; 866 reg = <0x0 0x2a80000 0x0 0x1000>; 867 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 869 clock-names = "ipg", "per"; 870 big-endian; 871 }; 872 873 can2: can@2a90000 { 874 compatible = "fsl,ls1021ar2-flexcan"; 875 reg = <0x0 0x2a90000 0x0 0x1000>; 876 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 878 clock-names = "ipg", "per"; 879 big-endian; 880 }; 881 882 can3: can@2aa0000 { 883 compatible = "fsl,ls1021ar2-flexcan"; 884 reg = <0x0 0x2aa0000 0x0 0x1000>; 885 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 887 clock-names = "ipg", "per"; 888 big-endian; 889 }; 890 891 ocram1: sram@10000000 { 892 compatible = "mmio-sram"; 893 reg = <0x0 0x10000000 0x0 0x10000>; 894 #address-cells = <1>; 895 #size-cells = <1>; 896 ranges = <0x0 0x0 0x10000000 0x10000>; 897 }; 898 899 ocram2: sram@10010000 { 900 compatible = "mmio-sram"; 901 reg = <0x0 0x10010000 0x0 0x10000>; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 ranges = <0x0 0x0 0x10010000 0x10000>; 905 }; 906 907 qdma: dma-controller@8390000 { 908 compatible = "fsl,ls1021a-qdma"; 909 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 910 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 911 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 912 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "qdma-error", 916 "qdma-queue0", "qdma-queue1"; 917 #dma-cells = <2>; 918 dma-channels = <8>; 919 block-number = <1>; 920 block-offset = <0x1000>; 921 fsl,dma-queues = <2>; 922 status-sizes = <64>; 923 queue-sizes = <64 64>; 924 big-endian; 925 }; 926 927 rcpm: power-controller@1ee2140 { 928 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; 929 reg = <0x0 0x1ee2140 0x0 0x8>; 930 #fsl,rcpm-wakeup-cells = <2>; 931 #power-domain-cells = <0>; 932 }; 933 934 ftm_alarm0: timer0@29d0000 { 935 compatible = "fsl,ls1021a-ftm-alarm"; 936 reg = <0x0 0x29d0000 0x0 0x10000>; 937 reg-names = "ftm"; 938 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; 939 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 940 big-endian; 941 }; 942 }; 943 944 thermal-zones { 945 cpu_thermal: cpu-thermal { 946 polling-delay-passive = <1000>; 947 polling-delay = <5000>; 948 949 thermal-sensors = <&tmu 0>; 950 951 trips { 952 cpu_alert: cpu-alert { 953 temperature = <85000>; 954 hysteresis = <2000>; 955 type = "passive"; 956 }; 957 cpu_crit: cpu-crit { 958 temperature = <95000>; 959 hysteresis = <2000>; 960 type = "critical"; 961 }; 962 }; 963 964 cooling-maps { 965 map0 { 966 trip = <&cpu_alert>; 967 cooling-device = 968 <&cpu0 THERMAL_NO_LIMIT 969 THERMAL_NO_LIMIT>, 970 <&cpu1 THERMAL_NO_LIMIT 971 THERMAL_NO_LIMIT>; 972 }; 973 }; 974 }; 975 }; 976};