cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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meson8.dtsi (17711B)


      1// SPDX-License-Identifier: GPL-2.0 OR MIT
      2/*
      3 * Copyright 2014 Carlo Caione <carlo@caione.org>
      4 */
      5
      6#include <dt-bindings/clock/meson8-ddr-clkc.h>
      7#include <dt-bindings/clock/meson8b-clkc.h>
      8#include <dt-bindings/gpio/meson8-gpio.h>
      9#include <dt-bindings/power/meson8-power.h>
     10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
     11#include <dt-bindings/reset/amlogic,meson8b-reset.h>
     12#include <dt-bindings/thermal/thermal.h>
     13#include "meson.dtsi"
     14
     15/ {
     16	model = "Amlogic Meson8 SoC";
     17	compatible = "amlogic,meson8";
     18
     19	cpus {
     20		#address-cells = <1>;
     21		#size-cells = <0>;
     22
     23		cpu0: cpu@200 {
     24			device_type = "cpu";
     25			compatible = "arm,cortex-a9";
     26			next-level-cache = <&L2>;
     27			reg = <0x200>;
     28			enable-method = "amlogic,meson8-smp";
     29			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
     30			operating-points-v2 = <&cpu_opp_table>;
     31			clocks = <&clkc CLKID_CPUCLK>;
     32			#cooling-cells = <2>; /* min followed by max */
     33		};
     34
     35		cpu1: cpu@201 {
     36			device_type = "cpu";
     37			compatible = "arm,cortex-a9";
     38			next-level-cache = <&L2>;
     39			reg = <0x201>;
     40			enable-method = "amlogic,meson8-smp";
     41			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
     42			operating-points-v2 = <&cpu_opp_table>;
     43			clocks = <&clkc CLKID_CPUCLK>;
     44			#cooling-cells = <2>; /* min followed by max */
     45		};
     46
     47		cpu2: cpu@202 {
     48			device_type = "cpu";
     49			compatible = "arm,cortex-a9";
     50			next-level-cache = <&L2>;
     51			reg = <0x202>;
     52			enable-method = "amlogic,meson8-smp";
     53			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
     54			operating-points-v2 = <&cpu_opp_table>;
     55			clocks = <&clkc CLKID_CPUCLK>;
     56			#cooling-cells = <2>; /* min followed by max */
     57		};
     58
     59		cpu3: cpu@203 {
     60			device_type = "cpu";
     61			compatible = "arm,cortex-a9";
     62			next-level-cache = <&L2>;
     63			reg = <0x203>;
     64			enable-method = "amlogic,meson8-smp";
     65			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
     66			operating-points-v2 = <&cpu_opp_table>;
     67			clocks = <&clkc CLKID_CPUCLK>;
     68			#cooling-cells = <2>; /* min followed by max */
     69		};
     70	};
     71
     72	cpu_opp_table: opp-table {
     73		compatible = "operating-points-v2";
     74		opp-shared;
     75
     76		opp-96000000 {
     77			opp-hz = /bits/ 64 <96000000>;
     78			opp-microvolt = <825000>;
     79		};
     80		opp-192000000 {
     81			opp-hz = /bits/ 64 <192000000>;
     82			opp-microvolt = <825000>;
     83		};
     84		opp-312000000 {
     85			opp-hz = /bits/ 64 <312000000>;
     86			opp-microvolt = <825000>;
     87		};
     88		opp-408000000 {
     89			opp-hz = /bits/ 64 <408000000>;
     90			opp-microvolt = <825000>;
     91		};
     92		opp-504000000 {
     93			opp-hz = /bits/ 64 <504000000>;
     94			opp-microvolt = <825000>;
     95		};
     96		opp-600000000 {
     97			opp-hz = /bits/ 64 <600000000>;
     98			opp-microvolt = <850000>;
     99		};
    100		opp-720000000 {
    101			opp-hz = /bits/ 64 <720000000>;
    102			opp-microvolt = <850000>;
    103		};
    104		opp-816000000 {
    105			opp-hz = /bits/ 64 <816000000>;
    106			opp-microvolt = <875000>;
    107		};
    108		opp-1008000000 {
    109			opp-hz = /bits/ 64 <1008000000>;
    110			opp-microvolt = <925000>;
    111		};
    112		opp-1200000000 {
    113			opp-hz = /bits/ 64 <1200000000>;
    114			opp-microvolt = <975000>;
    115		};
    116		opp-1416000000 {
    117			opp-hz = /bits/ 64 <1416000000>;
    118			opp-microvolt = <1025000>;
    119		};
    120		opp-1608000000 {
    121			opp-hz = /bits/ 64 <1608000000>;
    122			opp-microvolt = <1100000>;
    123		};
    124		opp-1800000000 {
    125			status = "disabled";
    126			opp-hz = /bits/ 64 <1800000000>;
    127			opp-microvolt = <1125000>;
    128		};
    129		opp-1992000000 {
    130			status = "disabled";
    131			opp-hz = /bits/ 64 <1992000000>;
    132			opp-microvolt = <1150000>;
    133		};
    134	};
    135
    136	gpu_opp_table: gpu-opp-table {
    137		compatible = "operating-points-v2";
    138
    139		opp-182142857 {
    140			opp-hz = /bits/ 64 <182142857>;
    141			opp-microvolt = <1150000>;
    142		};
    143		opp-318750000 {
    144			opp-hz = /bits/ 64 <318750000>;
    145			opp-microvolt = <1150000>;
    146		};
    147		opp-425000000 {
    148			opp-hz = /bits/ 64 <425000000>;
    149			opp-microvolt = <1150000>;
    150		};
    151		opp-510000000 {
    152			opp-hz = /bits/ 64 <510000000>;
    153			opp-microvolt = <1150000>;
    154		};
    155		opp-637500000 {
    156			opp-hz = /bits/ 64 <637500000>;
    157			opp-microvolt = <1150000>;
    158			turbo-mode;
    159		};
    160	};
    161
    162	pmu {
    163		compatible = "arm,cortex-a9-pmu";
    164		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
    165			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
    166			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
    167			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
    168		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
    169	};
    170
    171	reserved-memory {
    172		#address-cells = <1>;
    173		#size-cells = <1>;
    174		ranges;
    175
    176		/* 2 MiB reserved for Hardware ROM Firmware? */
    177		hwrom@0 {
    178			reg = <0x0 0x200000>;
    179			no-map;
    180		};
    181
    182		/*
    183		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
    184		 * code which is responsible for system suspend. It loads a
    185		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
    186		 * into SRAM, executes that and shuts down the (last) ARM core.
    187		 * The arc_power firmware then checks various wakeup sources
    188		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
    189		 * simply the power key) and re-starts the ARM core once it
    190		 * detects a wakeup request.
    191		 */
    192		power-firmware@4f00000 {
    193			reg = <0x4f00000 0x100000>;
    194			no-map;
    195		};
    196	};
    197
    198	thermal-zones {
    199		soc {
    200			polling-delay-passive = <250>; /* milliseconds */
    201			polling-delay = <1000>; /* milliseconds */
    202			thermal-sensors = <&thermal_sensor>;
    203
    204			cooling-maps {
    205				map0 {
    206					trip = <&soc_passive>;
    207					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    208							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    209							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    210							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    211							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    212				};
    213
    214				map1 {
    215					trip = <&soc_hot>;
    216					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    217							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    218							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    219							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
    220							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    221				};
    222			};
    223
    224			trips {
    225				soc_passive: soc-passive {
    226					temperature = <80000>; /* millicelsius */
    227					hysteresis = <2000>; /* millicelsius */
    228					type = "passive";
    229				};
    230
    231				soc_hot: soc-hot {
    232					temperature = <90000>; /* millicelsius */
    233					hysteresis = <2000>; /* millicelsius */
    234					type = "hot";
    235				};
    236
    237				soc_critical: soc-critical {
    238					temperature = <110000>; /* millicelsius */
    239					hysteresis = <2000>; /* millicelsius */
    240					type = "critical";
    241				};
    242			};
    243		};
    244	};
    245
    246	mmcbus: bus@c8000000 {
    247		compatible = "simple-bus";
    248		reg = <0xc8000000 0x8000>;
    249		#address-cells = <1>;
    250		#size-cells = <1>;
    251		ranges = <0x0 0xc8000000 0x8000>;
    252
    253		ddr_clkc: clock-controller@400 {
    254			compatible = "amlogic,meson8-ddr-clkc";
    255			reg = <0x400 0x20>;
    256			clocks = <&xtal>;
    257			clock-names = "xtal";
    258			#clock-cells = <1>;
    259		};
    260
    261		dmcbus: bus@6000 {
    262			compatible = "simple-bus";
    263			reg = <0x6000 0x400>;
    264			#address-cells = <1>;
    265			#size-cells = <1>;
    266			ranges = <0x0 0x6000 0x400>;
    267
    268			canvas: video-lut@20 {
    269				compatible = "amlogic,meson8-canvas",
    270					     "amlogic,canvas";
    271				reg = <0x20 0x14>;
    272			};
    273		};
    274	};
    275
    276	apb: bus@d0000000 {
    277		compatible = "simple-bus";
    278		reg = <0xd0000000 0x200000>;
    279		#address-cells = <1>;
    280		#size-cells = <1>;
    281		ranges = <0x0 0xd0000000 0x200000>;
    282
    283		mali: gpu@c0000 {
    284			compatible = "amlogic,meson8-mali", "arm,mali-450";
    285			reg = <0xc0000 0x40000>;
    286			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
    287				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
    288				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
    289				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
    290				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
    291				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
    292				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
    293				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
    294				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
    295				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
    296				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
    297				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
    298				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
    299				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
    300				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
    301				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
    302			interrupt-names = "gp", "gpmmu", "pp", "pmu",
    303					  "pp0", "ppmmu0", "pp1", "ppmmu1",
    304					  "pp2", "ppmmu2", "pp4", "ppmmu4",
    305					  "pp5", "ppmmu5", "pp6", "ppmmu6";
    306			resets = <&reset RESET_MALI>;
    307
    308			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
    309			clock-names = "bus", "core";
    310
    311			assigned-clocks = <&clkc CLKID_MALI>;
    312			assigned-clock-rates = <318750000>;
    313
    314			operating-points-v2 = <&gpu_opp_table>;
    315			#cooling-cells = <2>; /* min followed by max */
    316		};
    317	};
    318}; /* end of / */
    319
    320&aiu {
    321	compatible = "amlogic,aiu-meson8", "amlogic,aiu";
    322	clocks = <&clkc CLKID_AIU_GLUE>,
    323		 <&clkc CLKID_I2S_OUT>,
    324		 <&clkc CLKID_AOCLK_GATE>,
    325		 <&clkc CLKID_CTS_AMCLK>,
    326		 <&clkc CLKID_MIXER_IFACE>,
    327		 <&clkc CLKID_IEC958>,
    328		 <&clkc CLKID_IEC958_GATE>,
    329		 <&clkc CLKID_CTS_MCLK_I958>,
    330		 <&clkc CLKID_CTS_I958>;
    331	clock-names = "pclk",
    332		      "i2s_pclk",
    333		      "i2s_aoclk",
    334		      "i2s_mclk",
    335		      "i2s_mixer",
    336		      "spdif_pclk",
    337		      "spdif_aoclk",
    338		      "spdif_mclk",
    339		      "spdif_mclk_sel";
    340	resets = <&reset RESET_AIU>;
    341};
    342
    343&aobus {
    344	pmu: pmu@e0 {
    345		compatible = "amlogic,meson8-pmu", "syscon";
    346		reg = <0xe0 0x18>;
    347	};
    348
    349	pinctrl_aobus: pinctrl@84 {
    350		compatible = "amlogic,meson8-aobus-pinctrl";
    351		reg = <0x84 0xc>;
    352		#address-cells = <1>;
    353		#size-cells = <1>;
    354		ranges;
    355
    356		gpio_ao: ao-bank@14 {
    357			reg = <0x14 0x4>,
    358			      <0x2c 0x4>,
    359			      <0x24 0x8>;
    360			reg-names = "mux", "pull", "gpio";
    361			gpio-controller;
    362			#gpio-cells = <2>;
    363			gpio-ranges = <&pinctrl_aobus 0 0 16>;
    364		};
    365
    366		i2s_am_clk_pins: i2s-am-clk-out {
    367			mux {
    368				groups = "i2s_am_clk_out_ao";
    369				function = "i2s_ao";
    370				bias-disable;
    371			};
    372		};
    373
    374		i2s_out_ao_clk_pins: i2s-ao-clk-out {
    375			mux {
    376				groups = "i2s_ao_clk_out_ao";
    377				function = "i2s_ao";
    378				bias-disable;
    379			};
    380		};
    381
    382		i2s_out_lr_clk_pins: i2s-lr-clk-out {
    383			mux {
    384				groups = "i2s_lr_clk_out_ao";
    385				function = "i2s_ao";
    386				bias-disable;
    387			};
    388		};
    389
    390		i2s_out_ch01_ao_pins: i2s-out-ch01 {
    391			mux {
    392				groups = "i2s_out_ch01_ao";
    393				function = "i2s_ao";
    394				bias-disable;
    395			};
    396		};
    397
    398		uart_ao_a_pins: uart_ao_a {
    399			mux {
    400				groups = "uart_tx_ao_a", "uart_rx_ao_a";
    401				function = "uart_ao";
    402				bias-disable;
    403			};
    404		};
    405
    406		i2c_ao_pins: i2c_mst_ao {
    407			mux {
    408				groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
    409				function = "i2c_mst_ao";
    410				bias-disable;
    411			};
    412		};
    413
    414		ir_recv_pins: remote {
    415			mux {
    416				groups = "remote_input";
    417				function = "remote";
    418				bias-disable;
    419			};
    420		};
    421
    422		pwm_f_ao_pins: pwm-f-ao {
    423			mux {
    424				groups = "pwm_f_ao";
    425				function = "pwm_f_ao";
    426				bias-disable;
    427			};
    428		};
    429	};
    430};
    431
    432&ao_arc_rproc {
    433	compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
    434	amlogic,secbus2 = <&secbus2>;
    435	sram = <&ao_arc_sram>;
    436	resets = <&reset RESET_MEDIA_CPU>;
    437	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
    438};
    439
    440&cbus {
    441	reset: reset-controller@4404 {
    442		compatible = "amlogic,meson8b-reset";
    443		reg = <0x4404 0x9c>;
    444		#reset-cells = <1>;
    445	};
    446
    447	analog_top: analog-top@81a8 {
    448		compatible = "amlogic,meson8-analog-top", "syscon";
    449		reg = <0x81a8 0x14>;
    450	};
    451
    452	pwm_ef: pwm@86c0 {
    453		compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
    454		reg = <0x86c0 0x10>;
    455		#pwm-cells = <3>;
    456		status = "disabled";
    457	};
    458
    459	clock-measure@8758 {
    460		compatible = "amlogic,meson8-clk-measure";
    461		reg = <0x8758 0x1c>;
    462	};
    463
    464	pinctrl_cbus: pinctrl@9880 {
    465		compatible = "amlogic,meson8-cbus-pinctrl";
    466		reg = <0x9880 0x10>;
    467		#address-cells = <1>;
    468		#size-cells = <1>;
    469		ranges;
    470
    471		gpio: banks@80b0 {
    472			reg = <0x80b0 0x28>,
    473			      <0x80e8 0x18>,
    474			      <0x8120 0x18>,
    475			      <0x8030 0x30>;
    476			reg-names = "mux", "pull", "pull-enable", "gpio";
    477			gpio-controller;
    478			#gpio-cells = <2>;
    479			gpio-ranges = <&pinctrl_cbus 0 0 120>;
    480		};
    481
    482		sd_a_pins: sd-a {
    483			mux {
    484				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
    485					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
    486				function = "sd_a";
    487				bias-disable;
    488			};
    489		};
    490
    491		sd_b_pins: sd-b {
    492			mux {
    493				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
    494					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
    495				function = "sd_b";
    496				bias-disable;
    497			};
    498		};
    499
    500		sd_c_pins: sd-c {
    501			mux {
    502				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
    503					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
    504				function = "sd_c";
    505				bias-disable;
    506			};
    507		};
    508
    509		sdxc_b_pins: sdxc-b {
    510			mux {
    511				groups = "sdxc_d0_b", "sdxc_d13_b",
    512					 "sdxc_clk_b", "sdxc_cmd_b";
    513				function = "sdxc_b";
    514				bias-pull-up;
    515			};
    516		};
    517
    518		spdif_out_pins: spdif-out {
    519			mux {
    520				groups = "spdif_out";
    521				function = "spdif";
    522				bias-disable;
    523			};
    524		};
    525
    526		spi_nor_pins: nor {
    527			mux {
    528				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
    529				function = "nor";
    530				bias-disable;
    531			};
    532		};
    533
    534		eth_pins: ethernet {
    535			mux {
    536				groups = "eth_tx_clk_50m", "eth_tx_en",
    537					 "eth_txd1", "eth_txd0",
    538					 "eth_rx_clk_in", "eth_rx_dv",
    539					 "eth_rxd1", "eth_rxd0", "eth_mdio",
    540					 "eth_mdc";
    541				function = "ethernet";
    542				bias-disable;
    543			};
    544		};
    545
    546		pwm_e_pins: pwm-e {
    547			mux {
    548				groups = "pwm_e";
    549				function = "pwm_e";
    550				bias-disable;
    551			};
    552		};
    553
    554		uart_a1_pins: uart-a1 {
    555			mux {
    556				groups = "uart_tx_a1",
    557				       "uart_rx_a1";
    558				function = "uart_a";
    559				bias-disable;
    560			};
    561		};
    562
    563		uart_a1_cts_rts_pins: uart-a1-cts-rts {
    564			mux {
    565				groups = "uart_cts_a1",
    566				       "uart_rts_a1";
    567				function = "uart_a";
    568				bias-disable;
    569			};
    570		};
    571	};
    572};
    573
    574&ahb_sram {
    575	ao_arc_sram: ao-arc-sram@0 {
    576		compatible = "amlogic,meson8-ao-arc-sram";
    577		reg = <0x0 0x8000>;
    578		pool;
    579	};
    580
    581	smp-sram@1ff80 {
    582		compatible = "amlogic,meson8-smp-sram";
    583		reg = <0x1ff80 0x8>;
    584	};
    585};
    586
    587&efuse {
    588	compatible = "amlogic,meson8-efuse";
    589	clocks = <&clkc CLKID_EFUSE>;
    590	clock-names = "core";
    591
    592	temperature_calib: calib@1f4 {
    593		/* only the upper two bytes are relevant */
    594		reg = <0x1f4 0x4>;
    595	};
    596};
    597
    598&ethmac {
    599	clocks = <&clkc CLKID_ETH>;
    600	clock-names = "stmmaceth";
    601
    602	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
    603};
    604
    605&gpio_intc {
    606	compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
    607	status = "okay";
    608};
    609
    610&hhi {
    611	clkc: clock-controller {
    612		compatible = "amlogic,meson8-clkc";
    613		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
    614		clock-names = "xtal", "ddr_pll";
    615		#clock-cells = <1>;
    616		#reset-cells = <1>;
    617	};
    618
    619	pwrc: power-controller {
    620		compatible = "amlogic,meson8-pwrc";
    621		#power-domain-cells = <1>;
    622		amlogic,ao-sysctrl = <&pmu>;
    623		clocks = <&clkc CLKID_VPU>;
    624		clock-names = "vpu";
    625		assigned-clocks = <&clkc CLKID_VPU>;
    626		assigned-clock-rates = <364285714>;
    627	};
    628};
    629
    630&hwrng {
    631	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
    632	clocks = <&clkc CLKID_RNG0>;
    633	clock-names = "core";
    634};
    635
    636&i2c_AO {
    637	clocks = <&clkc CLKID_CLK81>;
    638};
    639
    640&i2c_A {
    641	clocks = <&clkc CLKID_CLK81>;
    642};
    643
    644&i2c_B {
    645	clocks = <&clkc CLKID_CLK81>;
    646};
    647
    648&L2 {
    649	arm,data-latency = <3 3 3>;
    650	arm,tag-latency = <2 2 2>;
    651	arm,filter-ranges = <0x100000 0xc0000000>;
    652	prefetch-data = <1>;
    653	prefetch-instr = <1>;
    654	arm,shared-override;
    655};
    656
    657&periph {
    658	scu@0 {
    659		compatible = "arm,cortex-a9-scu";
    660		reg = <0x0 0x100>;
    661	};
    662
    663	timer@200 {
    664		compatible = "arm,cortex-a9-global-timer";
    665		reg = <0x200 0x20>;
    666		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
    667		clocks = <&clkc CLKID_PERIPH>;
    668
    669		/*
    670		 * the arm_global_timer driver currently does not handle clock
    671		 * rate changes. Keep it disabled for now.
    672		 */
    673		status = "disabled";
    674	};
    675
    676	timer@600 {
    677		compatible = "arm,cortex-a9-twd-timer";
    678		reg = <0x600 0x20>;
    679		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
    680		clocks = <&clkc CLKID_PERIPH>;
    681	};
    682};
    683
    684&pwm_ab {
    685	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
    686};
    687
    688&pwm_cd {
    689	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
    690};
    691
    692&rtc {
    693	compatible = "amlogic,meson8-rtc";
    694	resets = <&reset RESET_RTC>;
    695};
    696
    697&saradc {
    698	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
    699	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
    700	clock-names = "clkin", "core";
    701	amlogic,hhi-sysctrl = <&hhi>;
    702	nvmem-cells = <&temperature_calib>;
    703	nvmem-cell-names = "temperature_calib";
    704};
    705
    706&sdhc {
    707	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
    708	clocks = <&xtal>,
    709		 <&clkc CLKID_FCLK_DIV4>,
    710		 <&clkc CLKID_FCLK_DIV3>,
    711		 <&clkc CLKID_FCLK_DIV5>,
    712		 <&clkc CLKID_SDHC>;
    713	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
    714};
    715
    716&secbus {
    717	secbus2: system-controller@4000 {
    718		compatible = "amlogic,meson8-secbus2", "syscon";
    719		reg = <0x4000 0x2000>;
    720	};
    721};
    722
    723&sdio {
    724	compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
    725	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
    726	clock-names = "core", "clkin";
    727};
    728
    729&spifc {
    730	clocks = <&clkc CLKID_CLK81>;
    731};
    732
    733&timer_abcde {
    734	clocks = <&xtal>, <&clkc CLKID_CLK81>;
    735	clock-names = "xtal", "pclk";
    736};
    737
    738&uart_AO {
    739	compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
    740	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
    741	clock-names = "xtal", "pclk", "baud";
    742};
    743
    744&uart_A {
    745	compatible = "amlogic,meson8-uart";
    746	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
    747	clock-names = "xtal", "pclk", "baud";
    748};
    749
    750&uart_B {
    751	compatible = "amlogic,meson8-uart";
    752	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
    753	clock-names = "xtal", "pclk", "baud";
    754};
    755
    756&uart_C {
    757	compatible = "amlogic,meson8-uart";
    758	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
    759	clock-names = "xtal", "pclk", "baud";
    760};
    761
    762&usb0 {
    763	compatible = "amlogic,meson8-usb", "snps,dwc2";
    764	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
    765	clock-names = "otg";
    766};
    767
    768&usb1 {
    769	compatible = "amlogic,meson8-usb", "snps,dwc2";
    770	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
    771	clock-names = "otg";
    772};
    773
    774&usb0_phy {
    775	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
    776	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
    777	clock-names = "usb_general", "usb";
    778	resets = <&reset RESET_USB_OTG>;
    779};
    780
    781&usb1_phy {
    782	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
    783	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
    784	clock-names = "usb_general", "usb";
    785	resets = <&reset RESET_USB_OTG>;
    786};