cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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meson8b-odroidc1.dts (8281B)


      1// SPDX-License-Identifier: GPL-2.0 OR MIT
      2/*
      3 * Copyright 2015 Endless Mobile, Inc.
      4 * Author: Carlo Caione <carlo@endlessm.com>
      5 */
      6
      7/dts-v1/;
      8#include "meson8b.dtsi"
      9#include <dt-bindings/gpio/gpio.h>
     10
     11/ {
     12	model = "Hardkernel ODROID-C1";
     13	compatible = "hardkernel,odroid-c1", "amlogic,meson8b";
     14
     15	aliases {
     16		serial0 = &uart_AO;
     17		mmc0 = &sd_card_slot;
     18		mmc1 = &sdhc;
     19	};
     20
     21	chosen {
     22		stdout-path = "serial0:115200n8";
     23	};
     24
     25	memory {
     26		device_type = "memory";
     27		reg = <0x40000000 0x40000000>;
     28	};
     29
     30	emmc_pwrseq: emmc-pwrseq {
     31		compatible = "mmc-pwrseq-emmc";
     32		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
     33	};
     34
     35	leds {
     36		compatible = "gpio-leds";
     37		blue {
     38			label = "c1:blue:alive";
     39			gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
     40			linux,default-trigger = "heartbeat";
     41			default-state = "off";
     42		};
     43	};
     44
     45	p5v0: regulator-p5v0 {
     46		compatible = "regulator-fixed";
     47
     48		regulator-name = "P5V0";
     49		regulator-min-microvolt = <5000000>;
     50		regulator-max-microvolt = <5000000>;
     51	};
     52
     53	tflash_vdd: regulator-tflash_vdd {
     54		/*
     55		 * signal name from schematics: TFLASH_VDD_EN
     56		 */
     57		compatible = "regulator-fixed";
     58
     59		regulator-name = "TFLASH_VDD";
     60		regulator-min-microvolt = <3300000>;
     61		regulator-max-microvolt = <3300000>;
     62
     63		vin-supply = <&vcc_3v3>;
     64
     65		gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
     66		enable-active-high;
     67	};
     68
     69	tf_io: gpio-regulator-tf_io {
     70		compatible = "regulator-gpio";
     71
     72		regulator-name = "TF_IO";
     73		regulator-min-microvolt = <1800000>;
     74		regulator-max-microvolt = <3300000>;
     75
     76		vin-supply = <&vcc_3v3>;
     77
     78		/*
     79		 * signal name from schematics: TF_3V3N_1V8_EN
     80		 */
     81		gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
     82		gpios-states = <0>;
     83
     84		states = <3300000 0
     85			  1800000 1>;
     86	};
     87
     88	rtc32k_xtal: rtc32k-xtal-clk {
     89		/* X3 in the schematics */
     90		compatible = "fixed-clock";
     91		clock-frequency = <32768>;
     92		clock-output-names = "RTC32K";
     93		#clock-cells = <0>;
     94	};
     95
     96	vcc_1v8: regulator-vcc-1v8 {
     97		/*
     98		 * RICHTEK RT9179 configured for a fixed output voltage of
     99		 * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and
    100		 * VDD1V8 according to the schematics.
    101		 */
    102		compatible = "regulator-fixed";
    103
    104		regulator-name = "VCC1V8";
    105		regulator-min-microvolt = <1800000>;
    106		regulator-max-microvolt = <1800000>;
    107
    108		vin-supply = <&p5v0>;
    109	};
    110
    111	vcc_3v3: regulator-vcc-3v3 {
    112		/*
    113		 * Monolithic Power Systems MP2161 configured for a fixed
    114		 * output voltage of 3.3V. This supplies not only VCC3V3 but
    115		 * also VDD3V3 and VDDIO_AO3V3 according to the schematics.
    116		 */
    117		compatible = "regulator-fixed";
    118
    119		regulator-name = "VCC3V3";
    120		regulator-min-microvolt = <3300000>;
    121		regulator-max-microvolt = <3300000>;
    122
    123		vin-supply = <&p5v0>;
    124	};
    125
    126	vcck: regulator-vcck {
    127		/* Monolithic Power Systems MP2161 */
    128		compatible = "pwm-regulator";
    129
    130		regulator-name = "VCCK";
    131		regulator-min-microvolt = <860000>;
    132		regulator-max-microvolt = <1140000>;
    133
    134		pwm-supply = <&p5v0>;
    135
    136		pwms = <&pwm_cd 0 12218 0>;
    137		pwm-dutycycle-range = <91 0>;
    138
    139		regulator-boot-on;
    140		regulator-always-on;
    141	};
    142
    143	vddc_ddr: regulator-vddc-ddr {
    144		/*
    145		 * Monolithic Power Systems MP2161 configured for a fixed
    146		 * output voltage of 1.5V. This supplies not only DDR_VDDC but
    147		 * also DDR3_1V5 according to the schematics.
    148		 */
    149		compatible = "regulator-fixed";
    150
    151		regulator-name = "DDR_VDDC";
    152		regulator-min-microvolt = <1500000>;
    153		regulator-max-microvolt = <1500000>;
    154
    155		vin-supply = <&p5v0>;
    156	};
    157
    158	vddee: regulator-vddee {
    159		/* Monolithic Power Systems MP2161 */
    160		compatible = "pwm-regulator";
    161
    162		regulator-name = "VDDEE";
    163		regulator-min-microvolt = <860000>;
    164		regulator-max-microvolt = <1140000>;
    165
    166		pwm-supply = <&p5v0>;
    167
    168		pwms = <&pwm_cd 1 12218 0>;
    169		pwm-dutycycle-range = <91 0>;
    170
    171		regulator-boot-on;
    172		regulator-always-on;
    173	};
    174
    175	vdd_rtc: regulator-vdd-rtc {
    176		/*
    177		 * Torex Semiconductor XC6215 configured for a fixed output of
    178		 * 0.9V.
    179		 */
    180		compatible = "regulator-fixed";
    181
    182		regulator-name = "VDD_RTC";
    183		regulator-min-microvolt = <900000>;
    184		regulator-max-microvolt = <900000>;
    185
    186		vin-supply = <&vcc_3v3>;
    187	};
    188};
    189
    190&cpu0 {
    191	cpu-supply = <&vcck>;
    192};
    193
    194&efuse {
    195	ethernet_mac_address: mac@1b4 {
    196		reg = <0x1b4 0x6>;
    197	};
    198};
    199
    200&ethmac {
    201	status = "okay";
    202
    203	pinctrl-0 = <&eth_rgmii_pins>;
    204	pinctrl-names = "default";
    205
    206	phy-handle = <&eth_phy>;
    207	phy-mode = "rgmii-id";
    208
    209	nvmem-cells = <&ethernet_mac_address>;
    210	nvmem-cell-names = "mac-address";
    211
    212	mdio {
    213		compatible = "snps,dwmac-mdio";
    214		#address-cells = <1>;
    215		#size-cells = <0>;
    216
    217		/* Realtek RTL8211F (0x001cc916) */
    218		eth_phy: ethernet-phy@0 {
    219			reg = <0>;
    220
    221			reset-assert-us = <10000>;
    222			reset-deassert-us = <80000>;
    223			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
    224
    225			interrupt-parent = <&gpio_intc>;
    226			/* GPIOH_3 */
    227			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
    228		};
    229	};
    230};
    231
    232&gpio {
    233	gpio-line-names = /* Bank GPIOX */
    234			  "J2 Header Pin 35", "J2 Header Pin 36",
    235			  "J2 Header Pin 32", "J2 Header Pin 31",
    236			  "J2 Header Pin 29", "J2 Header Pin 18",
    237			  "J2 Header Pin 22", "J2 Header Pin 16",
    238			  "J2 Header Pin 23", "J2 Header Pin 21",
    239			  "J2 Header Pin 19", "J2 Header Pin 33",
    240			  "J2 Header Pin 8", "J2 Header Pin 10",
    241			  "J2 Header Pin 15", "J2 Header Pin 13",
    242			  "J2 Header Pin 24", "J2 Header Pin 26",
    243			  /* Bank GPIOY */
    244			  "Revision (upper)", "Revision (lower)",
    245			  "J2 Header Pin 7", "", "J2 Header Pin 12",
    246			  "J2 Header Pin 11", "", "", "",
    247			  "TFLASH_VDD_EN", "", "",
    248			  /* Bank GPIODV */
    249			  "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL",
    250			  "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)",
    251			  "",
    252			  /* Bank GPIOH */
    253			  "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
    254			  "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1",
    255			  "ETH_TXD0", "ETH_TXD3", "ETH_TXD2",
    256			  "ETH_RGMII_TX_CLK",
    257			  /* Bank CARD */
    258			  "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)",
    259			  "SD_CLK",  "SD_CMD", "SD_DATA3 (SDB_D3)",
    260			  "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)",
    261			  /* Bank BOOT */
    262			  "SDC_D0 (EMMC)", "SDC_D1 (EMMC)",
    263			  "SDC_D2 (EMMC)", "SDC_D3 (EMMC)",
    264			  "SDC_D4 (EMMC)", "SDC_D5 (EMMC)",
    265			  "SDC_D6 (EMMC)", "SDC_D7 (EMMC)",
    266			  "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)",
    267			  "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "",
    268			  "", "", "", "",
    269			  /* Bank DIF */
    270			  "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV",
    271			  "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2",
    272			  "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT",
    273			  "ETH_MDC", "ETH_MDIO";
    274};
    275
    276&gpio_ao {
    277	gpio-line-names = "UART TX", "UART RX", "",
    278			  "TF_3V3N_1V8_EN", "USB_HUB_RST_N",
    279			  "USB_OTG_PWREN", "J7 Header Pin 2",
    280			  "IR_IN", "J7 Header Pin 4",
    281			  "J7 Header Pin 6", "J7 Header Pin 5",
    282			  "J7 Header Pin 7", "HDMI_CEC",
    283			  "SYS_LED", "", "";
    284
    285	/*
    286	 * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
    287	 * to be turned high in order to be detected by the USB Controller.
    288	 * This signal should be handled by a USB specific power sequence
    289	 * in order to reset the Hub when USB bus is powered down.
    290	 */
    291	usb-hub {
    292		gpio-hog;
    293		gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
    294		output-high;
    295		line-name = "usb-hub-reset";
    296	};
    297};
    298
    299&ir_receiver {
    300	status = "okay";
    301	pinctrl-0 = <&ir_recv_pins>;
    302	pinctrl-names = "default";
    303};
    304
    305&mali {
    306	mali-supply = <&vddee>;
    307};
    308
    309&saradc {
    310	status = "okay";
    311	vref-supply = <&vcc_1v8>;
    312};
    313
    314&sdhc {
    315	status = "okay";
    316
    317	pinctrl-0 = <&sdxc_c_pins>;
    318	pinctrl-names = "default";
    319
    320	bus-width = <8>;
    321	max-frequency = <100000000>;
    322
    323	disable-wp;
    324	cap-mmc-highspeed;
    325	mmc-hs200-1_8v;
    326	no-sdio;
    327
    328	mmc-pwrseq = <&emmc_pwrseq>;
    329
    330	vmmc-supply = <&vcc_3v3>;
    331	vqmmc-supply = <&vcc_1v8>;
    332};
    333
    334&sdio {
    335	status = "okay";
    336
    337	pinctrl-0 = <&sd_b_pins>;
    338	pinctrl-names = "default";
    339
    340	/* SD card */
    341	sd_card_slot: slot@1 {
    342		compatible = "mmc-slot";
    343		reg = <1>;
    344		status = "okay";
    345
    346		bus-width = <4>;
    347		no-sdio;
    348		cap-mmc-highspeed;
    349		cap-sd-highspeed;
    350		disable-wp;
    351
    352		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
    353
    354		vmmc-supply = <&tflash_vdd>;
    355		vqmmc-supply = <&tf_io>;
    356	};
    357};
    358
    359&pwm_cd {
    360	status = "okay";
    361	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
    362	pinctrl-names = "default";
    363	clocks = <&xtal>, <&xtal>;
    364	clock-names = "clkin0", "clkin1";
    365};
    366
    367&rtc {
    368	/* needs to be enabled manually when a battery is connected */
    369	clocks = <&rtc32k_xtal>;
    370	vdd-supply = <&vdd_rtc>;
    371};
    372
    373&uart_AO {
    374	status = "okay";
    375	pinctrl-0 = <&uart_ao_a_pins>;
    376	pinctrl-names = "default";
    377};
    378
    379&usb1_phy {
    380	status = "okay";
    381};
    382
    383&usb1 {
    384	status = "okay";
    385};