cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt6582.dtsi (2816B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru>
      4 */
      5
      6#include <dt-bindings/interrupt-controller/irq.h>
      7#include <dt-bindings/interrupt-controller/arm-gic.h>
      8
      9/ {
     10	#address-cells = <1>;
     11	#size-cells = <1>;
     12	compatible = "mediatek,mt6582";
     13	interrupt-parent = <&sysirq>;
     14
     15	cpus {
     16		#address-cells = <1>;
     17		#size-cells = <0>;
     18
     19		cpu@0 {
     20			device_type = "cpu";
     21			compatible = "arm,cortex-a7";
     22			reg = <0x0>;
     23		};
     24		cpu@1 {
     25			device_type = "cpu";
     26			compatible = "arm,cortex-a7";
     27			reg = <0x1>;
     28		};
     29		cpu@2 {
     30			device_type = "cpu";
     31			compatible = "arm,cortex-a7";
     32			reg = <0x2>;
     33		};
     34		cpu@3 {
     35			device_type = "cpu";
     36			compatible = "arm,cortex-a7";
     37			reg = <0x3>;
     38		};
     39	};
     40
     41	system_clk: dummy13m {
     42		compatible = "fixed-clock";
     43		clock-frequency = <13000000>;
     44		#clock-cells = <0>;
     45	};
     46
     47	rtc_clk: dummy32k {
     48		compatible = "fixed-clock";
     49		clock-frequency = <32000>;
     50		#clock-cells = <0>;
     51	};
     52
     53	uart_clk: dummy26m {
     54		compatible = "fixed-clock";
     55		clock-frequency = <26000000>;
     56		#clock-cells = <0>;
     57	};
     58
     59	timer: timer@11008000 {
     60		compatible = "mediatek,mt6577-timer";
     61		reg = <0x10008000 0x80>;
     62		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
     63		clocks = <&system_clk>, <&rtc_clk>;
     64		clock-names = "system-clk", "rtc-clk";
     65	};
     66
     67	sysirq: interrupt-controller@10200100 {
     68		compatible = "mediatek,mt6582-sysirq",
     69			     "mediatek,mt6577-sysirq";
     70		interrupt-controller;
     71		#interrupt-cells = <3>;
     72		interrupt-parent = <&gic>;
     73		reg = <0x10200100 0x1c>;
     74	};
     75
     76	gic: interrupt-controller@10211000 {
     77		compatible = "arm,cortex-a7-gic";
     78		interrupt-controller;
     79		#interrupt-cells = <3>;
     80		interrupt-parent = <&gic>;
     81		reg = <0x10211000 0x1000>,
     82		      <0x10212000 0x2000>,
     83		      <0x10214000 0x2000>,
     84		      <0x10216000 0x2000>;
     85	};
     86
     87	uart0: serial@11002000 {
     88		compatible = "mediatek,mt6582-uart",
     89			     "mediatek,mt6577-uart";
     90		reg = <0x11002000 0x400>;
     91		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
     92		clocks = <&uart_clk>;
     93		status = "disabled";
     94	};
     95
     96	uart1: serial@11003000 {
     97		compatible = "mediatek,mt6582-uart",
     98			     "mediatek,mt6577-uart";
     99		reg = <0x11003000 0x400>;
    100		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
    101		clocks = <&uart_clk>;
    102		status = "disabled";
    103	};
    104
    105	uart2: serial@11004000 {
    106		compatible = "mediatek,mt6582-uart",
    107			     "mediatek,mt6577-uart";
    108		reg = <0x11004000 0x400>;
    109		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
    110		clocks = <&uart_clk>;
    111		status = "disabled";
    112	};
    113
    114	uart3: serial@11005000 {
    115		compatible = "mediatek,mt6582-uart",
    116			     "mediatek,mt6577-uart";
    117		reg = <0x11005000 0x400>;
    118		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
    119		clocks = <&uart_clk>;
    120		status = "disabled";
    121	};
    122
    123	watchdog: watchdog@10007000 {
    124		compatible = "mediatek,mt6582-wdt",
    125			     "mediatek,mt6589-wdt";
    126		reg = <0x10007000 0x100>;
    127	};
    128};