cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt8127.dtsi (3724B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (c) 2014 MediaTek Inc.
      4 * Author: Joe.C <yingjoe.chen@mediatek.com>
      5 *
      6 */
      7
      8#include <dt-bindings/interrupt-controller/irq.h>
      9#include <dt-bindings/interrupt-controller/arm-gic.h>
     10
     11/ {
     12	#address-cells = <2>;
     13	#size-cells = <2>;
     14	compatible = "mediatek,mt8127";
     15	interrupt-parent = <&sysirq>;
     16
     17	cpus {
     18		#address-cells = <1>;
     19		#size-cells = <0>;
     20		enable-method = "mediatek,mt81xx-tz-smp";
     21
     22		cpu@0 {
     23			device_type = "cpu";
     24			compatible = "arm,cortex-a7";
     25			reg = <0x0>;
     26		};
     27		cpu@1 {
     28			device_type = "cpu";
     29			compatible = "arm,cortex-a7";
     30			reg = <0x1>;
     31		};
     32		cpu@2 {
     33			device_type = "cpu";
     34			compatible = "arm,cortex-a7";
     35			reg = <0x2>;
     36		};
     37		cpu@3 {
     38			device_type = "cpu";
     39			compatible = "arm,cortex-a7";
     40			reg = <0x3>;
     41		};
     42
     43	};
     44
     45	reserved-memory {
     46		#address-cells = <2>;
     47		#size-cells = <2>;
     48		ranges;
     49
     50		trustzone-bootinfo@80002000 {
     51			compatible = "mediatek,trustzone-bootinfo";
     52			reg = <0 0x80002000 0 0x1000>;
     53		};
     54	};
     55
     56	clocks {
     57		#address-cells = <2>;
     58		#size-cells = <2>;
     59		compatible = "simple-bus";
     60		ranges;
     61
     62		system_clk: dummy13m {
     63			compatible = "fixed-clock";
     64			clock-frequency = <13000000>;
     65			#clock-cells = <0>;
     66		};
     67
     68		rtc_clk: dummy32k {
     69			compatible = "fixed-clock";
     70			clock-frequency = <32000>;
     71			#clock-cells = <0>;
     72		};
     73
     74		uart_clk: dummy26m {
     75			compatible = "fixed-clock";
     76			clock-frequency = <26000000>;
     77			#clock-cells = <0>;
     78                };
     79	};
     80
     81	timer {
     82		compatible = "arm,armv7-timer";
     83		interrupt-parent = <&gic>;
     84		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
     85					  IRQ_TYPE_LEVEL_LOW)>,
     86			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
     87					  IRQ_TYPE_LEVEL_LOW)>,
     88			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
     89					  IRQ_TYPE_LEVEL_LOW)>,
     90			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
     91					  IRQ_TYPE_LEVEL_LOW)>;
     92		clock-frequency = <13000000>;
     93		arm,cpu-registers-not-fw-configured;
     94	};
     95
     96	soc {
     97		#address-cells = <2>;
     98		#size-cells = <2>;
     99		compatible = "simple-bus";
    100		ranges;
    101
    102		timer: timer@10008000 {
    103			compatible = "mediatek,mt8127-timer",
    104					"mediatek,mt6577-timer";
    105			reg = <0 0x10008000 0 0x80>;
    106			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
    107			clocks = <&system_clk>, <&rtc_clk>;
    108			clock-names = "system-clk", "rtc-clk";
    109		};
    110
    111		sysirq: interrupt-controller@10200100 {
    112			compatible = "mediatek,mt8127-sysirq",
    113				     "mediatek,mt6577-sysirq";
    114			interrupt-controller;
    115			#interrupt-cells = <3>;
    116			interrupt-parent = <&gic>;
    117			reg = <0 0x10200100 0 0x1c>;
    118		};
    119
    120		gic: interrupt-controller@10211000 {
    121			compatible = "arm,cortex-a7-gic";
    122			interrupt-controller;
    123			#interrupt-cells = <3>;
    124			interrupt-parent = <&gic>;
    125			reg = <0 0x10211000 0 0x1000>,
    126			      <0 0x10212000 0 0x2000>,
    127			      <0 0x10214000 0 0x2000>,
    128			      <0 0x10216000 0 0x2000>;
    129		};
    130
    131		uart0: serial@11002000 {
    132			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
    133			reg = <0 0x11002000 0 0x400>;
    134			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
    135			clocks = <&uart_clk>;
    136			status = "disabled";
    137		};
    138
    139		uart1: serial@11003000 {
    140			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
    141			reg = <0 0x11003000 0 0x400>;
    142			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
    143			clocks = <&uart_clk>;
    144			status = "disabled";
    145		};
    146
    147		uart2: serial@11004000 {
    148			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
    149			reg = <0 0x11004000 0 0x400>;
    150			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
    151			clocks = <&uart_clk>;
    152			status = "disabled";
    153		};
    154
    155		uart3: serial@11005000 {
    156			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
    157			reg = <0 0x11005000 0 0x400>;
    158			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
    159			clocks = <&uart_clk>;
    160			status = "disabled";
    161		};
    162	};
    163};