nuvoton-common-npcm7xx.dtsi (25938B)
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com 3// Copyright 2018 Google, Inc. 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 7#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&gic>; 13 14 /* external reference clock */ 15 clk_refclk: clk_refclk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 clock-frequency = <25000000>; 19 clock-output-names = "refclk"; 20 }; 21 22 /* external reference clock for cpu. float in normal operation */ 23 clk_sysbypck: clk_sysbypck { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <800000000>; 27 clock-output-names = "sysbypck"; 28 }; 29 30 /* external reference clock for MC. float in normal operation */ 31 clk_mcbypck: clk_mcbypck { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <800000000>; 35 clock-output-names = "mcbypck"; 36 }; 37 38 /* external clock signal rg1refck, supplied by the phy */ 39 clk_rg1refck: clk_rg1refck { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <125000000>; 43 clock-output-names = "clk_rg1refck"; 44 }; 45 46 /* external clock signal rg2refck, supplied by the phy */ 47 clk_rg2refck: clk_rg2refck { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <125000000>; 51 clock-output-names = "clk_rg2refck"; 52 }; 53 54 clk_xin: clk_xin { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <50000000>; 58 clock-output-names = "clk_xin"; 59 }; 60 61 soc { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "simple-bus"; 65 interrupt-parent = <&gic>; 66 ranges = <0x0 0xf0000000 0x00900000>; 67 68 scu: scu@3fe000 { 69 compatible = "arm,cortex-a9-scu"; 70 reg = <0x3fe000 0x1000>; 71 }; 72 73 l2: cache-controller@3fc000 { 74 compatible = "arm,pl310-cache"; 75 reg = <0x3fc000 0x1000>; 76 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 77 cache-unified; 78 cache-level = <2>; 79 clocks = <&clk NPCM7XX_CLK_AXI>; 80 arm,shared-override; 81 }; 82 83 gic: interrupt-controller@3ff000 { 84 compatible = "arm,cortex-a9-gic"; 85 interrupt-controller; 86 #interrupt-cells = <3>; 87 reg = <0x3ff000 0x1000>, 88 <0x3fe100 0x100>; 89 }; 90 91 gcr: gcr@800000 { 92 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; 93 reg = <0x800000 0x1000>; 94 }; 95 96 rst: rst@801000 { 97 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; 98 reg = <0x801000 0x6C>; 99 }; 100 }; 101 102 ahb { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "simple-bus"; 106 interrupt-parent = <&gic>; 107 ranges; 108 109 rstc: rstc@f0801000 { 110 compatible = "nuvoton,npcm750-reset"; 111 reg = <0xf0801000 0x70>; 112 #reset-cells = <2>; 113 }; 114 115 clk: clock-controller@f0801000 { 116 compatible = "nuvoton,npcm750-clk", "syscon"; 117 #clock-cells = <1>; 118 clock-controller; 119 reg = <0xf0801000 0x1000>; 120 clock-names = "refclk", "sysbypck", "mcbypck"; 121 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; 122 }; 123 124 gmac0: eth@f0802000 { 125 device_type = "network"; 126 compatible = "snps,dwmac"; 127 reg = <0xf0802000 0x2000>; 128 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "macirq"; 130 ethernet = <0>; 131 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; 132 clock-names = "stmmaceth", "clk_gmac"; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&rg1_pins 135 &rg1mdio_pins>; 136 status = "disabled"; 137 }; 138 139 ehci1: usb@f0806000 { 140 compatible = "nuvoton,npcm750-ehci"; 141 reg = <0xf0806000 0x1000>; 142 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 }; 145 146 fiu0: spi@fb000000 { 147 compatible = "nuvoton,npcm750-fiu"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0xfb000000 0x1000>; 151 reg-names = "control", "memory"; 152 clocks = <&clk NPCM7XX_CLK_SPI0>; 153 clock-names = "clk_spi0"; 154 status = "disabled"; 155 }; 156 157 fiu3: spi@c0000000 { 158 compatible = "nuvoton,npcm750-fiu"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 reg = <0xc0000000 0x1000>; 162 reg-names = "control", "memory"; 163 clocks = <&clk NPCM7XX_CLK_SPI3>; 164 clock-names = "clk_spi3"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&spi3_pins>; 167 status = "disabled"; 168 }; 169 170 fiux: spi@fb001000 { 171 compatible = "nuvoton,npcm750-fiu"; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 reg = <0xfb001000 0x1000>; 175 reg-names = "control", "memory"; 176 clocks = <&clk NPCM7XX_CLK_SPIX>; 177 clock-names = "clk_spix"; 178 status = "disabled"; 179 }; 180 181 apb { 182 #address-cells = <1>; 183 #size-cells = <1>; 184 compatible = "simple-bus"; 185 interrupt-parent = <&gic>; 186 ranges = <0x0 0xf0000000 0x00300000>; 187 188 lpc_kcs: lpc_kcs@7000 { 189 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; 190 reg = <0x7000 0x40>; 191 reg-io-width = <1>; 192 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0x0 0x7000 0x40>; 196 197 kcs1: kcs1@0 { 198 compatible = "nuvoton,npcm750-kcs-bmc"; 199 reg = <0x0 0x40>; 200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 201 kcs_chan = <1>; 202 status = "disabled"; 203 }; 204 205 kcs2: kcs2@0 { 206 compatible = "nuvoton,npcm750-kcs-bmc"; 207 reg = <0x0 0x40>; 208 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 209 kcs_chan = <2>; 210 status = "disabled"; 211 }; 212 213 kcs3: kcs3@0 { 214 compatible = "nuvoton,npcm750-kcs-bmc"; 215 reg = <0x0 0x40>; 216 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 217 kcs_chan = <3>; 218 status = "disabled"; 219 }; 220 }; 221 222 spi0: spi@200000 { 223 compatible = "nuvoton,npcm750-pspi"; 224 reg = <0x200000 0x1000>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pspi1_pins>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clk NPCM7XX_CLK_APB5>; 231 clock-names = "clk_apb5"; 232 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; 233 status = "disabled"; 234 }; 235 236 spi1: spi@201000 { 237 compatible = "nuvoton,npcm750-pspi"; 238 reg = <0x201000 0x1000>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pspi2_pins>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&clk NPCM7XX_CLK_APB5>; 245 clock-names = "clk_apb5"; 246 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; 247 status = "disabled"; 248 }; 249 250 timer0: timer@8000 { 251 compatible = "nuvoton,npcm750-timer"; 252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 253 reg = <0x8000 0x1C>; 254 clocks = <&clk NPCM7XX_CLK_TIMER>; 255 }; 256 257 watchdog0: watchdog@801C { 258 compatible = "nuvoton,npcm750-wdt"; 259 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 260 reg = <0x801C 0x4>; 261 status = "disabled"; 262 clocks = <&clk NPCM7XX_CLK_TIMER>; 263 }; 264 265 watchdog1: watchdog@901C { 266 compatible = "nuvoton,npcm750-wdt"; 267 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 268 reg = <0x901C 0x4>; 269 status = "disabled"; 270 clocks = <&clk NPCM7XX_CLK_TIMER>; 271 }; 272 273 watchdog2: watchdog@a01C { 274 compatible = "nuvoton,npcm750-wdt"; 275 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 276 reg = <0xa01C 0x4>; 277 status = "disabled"; 278 clocks = <&clk NPCM7XX_CLK_TIMER>; 279 }; 280 281 serial0: serial@1000 { 282 compatible = "nuvoton,npcm750-uart"; 283 reg = <0x1000 0x1000>; 284 clocks = <&clk NPCM7XX_CLK_UART>; 285 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 286 reg-shift = <2>; 287 status = "disabled"; 288 }; 289 290 serial1: serial@2000 { 291 compatible = "nuvoton,npcm750-uart"; 292 reg = <0x2000 0x1000>; 293 clocks = <&clk NPCM7XX_CLK_UART>; 294 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 295 reg-shift = <2>; 296 status = "disabled"; 297 }; 298 299 serial2: serial@3000 { 300 compatible = "nuvoton,npcm750-uart"; 301 reg = <0x3000 0x1000>; 302 clocks = <&clk NPCM7XX_CLK_UART>; 303 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 304 reg-shift = <2>; 305 status = "disabled"; 306 }; 307 308 serial3: serial@4000 { 309 compatible = "nuvoton,npcm750-uart"; 310 reg = <0x4000 0x1000>; 311 clocks = <&clk NPCM7XX_CLK_UART>; 312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 313 reg-shift = <2>; 314 status = "disabled"; 315 }; 316 317 rng: rng@b000 { 318 compatible = "nuvoton,npcm750-rng"; 319 reg = <0xb000 0x8>; 320 status = "disabled"; 321 }; 322 323 adc: adc@c000 { 324 compatible = "nuvoton,npcm750-adc"; 325 reg = <0xc000 0x8>; 326 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clk NPCM7XX_CLK_ADC>; 328 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; 329 status = "disabled"; 330 }; 331 332 pwm_fan: pwm-fan-controller@103000 { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 compatible = "nuvoton,npcm750-pwm-fan"; 336 reg = <0x103000 0x2000>, <0x180000 0x8000>; 337 reg-names = "pwm", "fan"; 338 clocks = <&clk NPCM7XX_CLK_APB3>, 339 <&clk NPCM7XX_CLK_APB4>; 340 clock-names = "pwm","fan"; 341 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pwm0_pins &pwm1_pins 351 &pwm2_pins &pwm3_pins 352 &pwm4_pins &pwm5_pins 353 &pwm6_pins &pwm7_pins 354 &fanin0_pins &fanin1_pins 355 &fanin2_pins &fanin3_pins 356 &fanin4_pins &fanin5_pins 357 &fanin6_pins &fanin7_pins 358 &fanin8_pins &fanin9_pins 359 &fanin10_pins &fanin11_pins 360 &fanin12_pins &fanin13_pins 361 &fanin14_pins &fanin15_pins>; 362 status = "disabled"; 363 }; 364 365 i2c0: i2c@80000 { 366 reg = <0x80000 0x1000>; 367 compatible = "nuvoton,npcm750-i2c"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 clocks = <&clk NPCM7XX_CLK_APB2>; 371 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&smb0_pins>; 374 status = "disabled"; 375 }; 376 377 i2c1: i2c@81000 { 378 reg = <0x81000 0x1000>; 379 compatible = "nuvoton,npcm750-i2c"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 clocks = <&clk NPCM7XX_CLK_APB2>; 383 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&smb1_pins>; 386 status = "disabled"; 387 }; 388 389 i2c2: i2c@82000 { 390 reg = <0x82000 0x1000>; 391 compatible = "nuvoton,npcm750-i2c"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 clocks = <&clk NPCM7XX_CLK_APB2>; 395 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&smb2_pins>; 398 status = "disabled"; 399 }; 400 401 i2c3: i2c@83000 { 402 reg = <0x83000 0x1000>; 403 compatible = "nuvoton,npcm750-i2c"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&clk NPCM7XX_CLK_APB2>; 407 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&smb3_pins>; 410 status = "disabled"; 411 }; 412 413 i2c4: i2c@84000 { 414 reg = <0x84000 0x1000>; 415 compatible = "nuvoton,npcm750-i2c"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&clk NPCM7XX_CLK_APB2>; 419 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&smb4_pins>; 422 status = "disabled"; 423 }; 424 425 i2c5: i2c@85000 { 426 reg = <0x85000 0x1000>; 427 compatible = "nuvoton,npcm750-i2c"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&clk NPCM7XX_CLK_APB2>; 431 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&smb5_pins>; 434 status = "disabled"; 435 }; 436 437 i2c6: i2c@86000 { 438 reg = <0x86000 0x1000>; 439 compatible = "nuvoton,npcm750-i2c"; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&clk NPCM7XX_CLK_APB2>; 443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&smb6_pins>; 446 status = "disabled"; 447 }; 448 449 i2c7: i2c@87000 { 450 reg = <0x87000 0x1000>; 451 compatible = "nuvoton,npcm750-i2c"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&clk NPCM7XX_CLK_APB2>; 455 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&smb7_pins>; 458 status = "disabled"; 459 }; 460 461 i2c8: i2c@88000 { 462 reg = <0x88000 0x1000>; 463 compatible = "nuvoton,npcm750-i2c"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clocks = <&clk NPCM7XX_CLK_APB2>; 467 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&smb8_pins>; 470 status = "disabled"; 471 }; 472 473 i2c9: i2c@89000 { 474 reg = <0x89000 0x1000>; 475 compatible = "nuvoton,npcm750-i2c"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 clocks = <&clk NPCM7XX_CLK_APB2>; 479 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&smb9_pins>; 482 status = "disabled"; 483 }; 484 485 i2c10: i2c@8a000 { 486 reg = <0x8a000 0x1000>; 487 compatible = "nuvoton,npcm750-i2c"; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&clk NPCM7XX_CLK_APB2>; 491 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&smb10_pins>; 494 status = "disabled"; 495 }; 496 497 i2c11: i2c@8b000 { 498 reg = <0x8b000 0x1000>; 499 compatible = "nuvoton,npcm750-i2c"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&clk NPCM7XX_CLK_APB2>; 503 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&smb11_pins>; 506 status = "disabled"; 507 }; 508 509 i2c12: i2c@8c000 { 510 reg = <0x8c000 0x1000>; 511 compatible = "nuvoton,npcm750-i2c"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 clocks = <&clk NPCM7XX_CLK_APB2>; 515 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&smb12_pins>; 518 status = "disabled"; 519 }; 520 521 i2c13: i2c@8d000 { 522 reg = <0x8d000 0x1000>; 523 compatible = "nuvoton,npcm750-i2c"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&clk NPCM7XX_CLK_APB2>; 527 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&smb13_pins>; 530 status = "disabled"; 531 }; 532 533 i2c14: i2c@8e000 { 534 reg = <0x8e000 0x1000>; 535 compatible = "nuvoton,npcm750-i2c"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 clocks = <&clk NPCM7XX_CLK_APB2>; 539 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&smb14_pins>; 542 status = "disabled"; 543 }; 544 545 i2c15: i2c@8f000 { 546 reg = <0x8f000 0x1000>; 547 compatible = "nuvoton,npcm750-i2c"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clocks = <&clk NPCM7XX_CLK_APB2>; 551 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&smb15_pins>; 554 status = "disabled"; 555 }; 556 }; 557 }; 558 559 pinctrl: pinctrl@f0800000 { 560 #address-cells = <1>; 561 #size-cells = <1>; 562 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; 563 ranges = <0 0xf0010000 0x8000>; 564 gpio0: gpio@f0010000 { 565 gpio-controller; 566 #gpio-cells = <2>; 567 reg = <0x0 0x80>; 568 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 569 gpio-ranges = <&pinctrl 0 0 32>; 570 }; 571 gpio1: gpio@f0011000 { 572 gpio-controller; 573 #gpio-cells = <2>; 574 reg = <0x1000 0x80>; 575 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 576 gpio-ranges = <&pinctrl 0 32 32>; 577 }; 578 gpio2: gpio@f0012000 { 579 gpio-controller; 580 #gpio-cells = <2>; 581 reg = <0x2000 0x80>; 582 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 583 gpio-ranges = <&pinctrl 0 64 32>; 584 }; 585 gpio3: gpio@f0013000 { 586 gpio-controller; 587 #gpio-cells = <2>; 588 reg = <0x3000 0x80>; 589 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 590 gpio-ranges = <&pinctrl 0 96 32>; 591 }; 592 gpio4: gpio@f0014000 { 593 gpio-controller; 594 #gpio-cells = <2>; 595 reg = <0x4000 0x80>; 596 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 597 gpio-ranges = <&pinctrl 0 128 32>; 598 }; 599 gpio5: gpio@f0015000 { 600 gpio-controller; 601 #gpio-cells = <2>; 602 reg = <0x5000 0x80>; 603 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 604 gpio-ranges = <&pinctrl 0 160 32>; 605 }; 606 gpio6: gpio@f0016000 { 607 gpio-controller; 608 #gpio-cells = <2>; 609 reg = <0x6000 0x80>; 610 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 611 gpio-ranges = <&pinctrl 0 192 32>; 612 }; 613 gpio7: gpio@f0017000 { 614 gpio-controller; 615 #gpio-cells = <2>; 616 reg = <0x7000 0x80>; 617 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 618 gpio-ranges = <&pinctrl 0 224 32>; 619 }; 620 621 iox1_pins: iox1-pins { 622 groups = "iox1"; 623 function = "iox1"; 624 }; 625 iox2_pins: iox2-pins { 626 groups = "iox2"; 627 function = "iox2"; 628 }; 629 smb1d_pins: smb1d-pins { 630 groups = "smb1d"; 631 function = "smb1d"; 632 }; 633 smb2d_pins: smb2d-pins { 634 groups = "smb2d"; 635 function = "smb2d"; 636 }; 637 lkgpo1_pins: lkgpo1-pins { 638 groups = "lkgpo1"; 639 function = "lkgpo1"; 640 }; 641 lkgpo2_pins: lkgpo2-pins { 642 groups = "lkgpo2"; 643 function = "lkgpo2"; 644 }; 645 ioxh_pins: ioxh-pins { 646 groups = "ioxh"; 647 function = "ioxh"; 648 }; 649 gspi_pins: gspi-pins { 650 groups = "gspi"; 651 function = "gspi"; 652 }; 653 smb5b_pins: smb5b-pins { 654 groups = "smb5b"; 655 function = "smb5b"; 656 }; 657 smb5c_pins: smb5c-pins { 658 groups = "smb5c"; 659 function = "smb5c"; 660 }; 661 lkgpo0_pins: lkgpo0-pins { 662 groups = "lkgpo0"; 663 function = "lkgpo0"; 664 }; 665 pspi2_pins: pspi2-pins { 666 groups = "pspi2"; 667 function = "pspi2"; 668 }; 669 smb4den_pins: smb4den-pins { 670 groups = "smb4den"; 671 function = "smb4den"; 672 }; 673 smb4b_pins: smb4b-pins { 674 groups = "smb4b"; 675 function = "smb4b"; 676 }; 677 smb4c_pins: smb4c-pins { 678 groups = "smb4c"; 679 function = "smb4c"; 680 }; 681 smb15_pins: smb15-pins { 682 groups = "smb15"; 683 function = "smb15"; 684 }; 685 smb4d_pins: smb4d-pins { 686 groups = "smb4d"; 687 function = "smb4d"; 688 }; 689 smb14_pins: smb14-pins { 690 groups = "smb14"; 691 function = "smb14"; 692 }; 693 smb5_pins: smb5-pins { 694 groups = "smb5"; 695 function = "smb5"; 696 }; 697 smb4_pins: smb4-pins { 698 groups = "smb4"; 699 function = "smb4"; 700 }; 701 smb3_pins: smb3-pins { 702 groups = "smb3"; 703 function = "smb3"; 704 }; 705 spi0cs1_pins: spi0cs1-pins { 706 groups = "spi0cs1"; 707 function = "spi0cs1"; 708 }; 709 spi0cs2_pins: spi0cs2-pins { 710 groups = "spi0cs2"; 711 function = "spi0cs2"; 712 }; 713 spi0cs3_pins: spi0cs3-pins { 714 groups = "spi0cs3"; 715 function = "spi0cs3"; 716 }; 717 smb3c_pins: smb3c-pins { 718 groups = "smb3c"; 719 function = "smb3c"; 720 }; 721 smb3b_pins: smb3b-pins { 722 groups = "smb3b"; 723 function = "smb3b"; 724 }; 725 bmcuart0a_pins: bmcuart0a-pins { 726 groups = "bmcuart0a"; 727 function = "bmcuart0a"; 728 }; 729 uart1_pins: uart1-pins { 730 groups = "uart1"; 731 function = "uart1"; 732 }; 733 jtag2_pins: jtag2-pins { 734 groups = "jtag2"; 735 function = "jtag2"; 736 }; 737 bmcuart1_pins: bmcuart1-pins { 738 groups = "bmcuart1"; 739 function = "bmcuart1"; 740 }; 741 uart2_pins: uart2-pins { 742 groups = "uart2"; 743 function = "uart2"; 744 }; 745 bmcuart0b_pins: bmcuart0b-pins { 746 groups = "bmcuart0b"; 747 function = "bmcuart0b"; 748 }; 749 r1err_pins: r1err-pins { 750 groups = "r1err"; 751 function = "r1err"; 752 }; 753 r1md_pins: r1md-pins { 754 groups = "r1md"; 755 function = "r1md"; 756 }; 757 smb3d_pins: smb3d-pins { 758 groups = "smb3d"; 759 function = "smb3d"; 760 }; 761 fanin0_pins: fanin0-pins { 762 groups = "fanin0"; 763 function = "fanin0"; 764 }; 765 fanin1_pins: fanin1-pins { 766 groups = "fanin1"; 767 function = "fanin1"; 768 }; 769 fanin2_pins: fanin2-pins { 770 groups = "fanin2"; 771 function = "fanin2"; 772 }; 773 fanin3_pins: fanin3-pins { 774 groups = "fanin3"; 775 function = "fanin3"; 776 }; 777 fanin4_pins: fanin4-pins { 778 groups = "fanin4"; 779 function = "fanin4"; 780 }; 781 fanin5_pins: fanin5-pins { 782 groups = "fanin5"; 783 function = "fanin5"; 784 }; 785 fanin6_pins: fanin6-pins { 786 groups = "fanin6"; 787 function = "fanin6"; 788 }; 789 fanin7_pins: fanin7-pins { 790 groups = "fanin7"; 791 function = "fanin7"; 792 }; 793 fanin8_pins: fanin8-pins { 794 groups = "fanin8"; 795 function = "fanin8"; 796 }; 797 fanin9_pins: fanin9-pins { 798 groups = "fanin9"; 799 function = "fanin9"; 800 }; 801 fanin10_pins: fanin10-pins { 802 groups = "fanin10"; 803 function = "fanin10"; 804 }; 805 fanin11_pins: fanin11-pins { 806 groups = "fanin11"; 807 function = "fanin11"; 808 }; 809 fanin12_pins: fanin12-pins { 810 groups = "fanin12"; 811 function = "fanin12"; 812 }; 813 fanin13_pins: fanin13-pins { 814 groups = "fanin13"; 815 function = "fanin13"; 816 }; 817 fanin14_pins: fanin14-pins { 818 groups = "fanin14"; 819 function = "fanin14"; 820 }; 821 fanin15_pins: fanin15-pins { 822 groups = "fanin15"; 823 function = "fanin15"; 824 }; 825 pwm0_pins: pwm0-pins { 826 groups = "pwm0"; 827 function = "pwm0"; 828 }; 829 pwm1_pins: pwm1-pins { 830 groups = "pwm1"; 831 function = "pwm1"; 832 }; 833 pwm2_pins: pwm2-pins { 834 groups = "pwm2"; 835 function = "pwm2"; 836 }; 837 pwm3_pins: pwm3-pins { 838 groups = "pwm3"; 839 function = "pwm3"; 840 }; 841 r2_pins: r2-pins { 842 groups = "r2"; 843 function = "r2"; 844 }; 845 r2err_pins: r2err-pins { 846 groups = "r2err"; 847 function = "r2err"; 848 }; 849 r2md_pins: r2md-pins { 850 groups = "r2md"; 851 function = "r2md"; 852 }; 853 ga20kbc_pins: ga20kbc-pins { 854 groups = "ga20kbc"; 855 function = "ga20kbc"; 856 }; 857 smb5d_pins: smb5d-pins { 858 groups = "smb5d"; 859 function = "smb5d"; 860 }; 861 lpc_pins: lpc-pins { 862 groups = "lpc"; 863 function = "lpc"; 864 }; 865 espi_pins: espi-pins { 866 groups = "espi"; 867 function = "espi"; 868 }; 869 rg1_pins: rg1-pins { 870 groups = "rg1"; 871 function = "rg1"; 872 }; 873 rg1mdio_pins: rg1mdio-pins { 874 groups = "rg1mdio"; 875 function = "rg1mdio"; 876 }; 877 rg2_pins: rg2-pins { 878 groups = "rg2"; 879 function = "rg2"; 880 }; 881 ddr_pins: ddr-pins { 882 groups = "ddr"; 883 function = "ddr"; 884 }; 885 smb0_pins: smb0-pins { 886 groups = "smb0"; 887 function = "smb0"; 888 }; 889 smb1_pins: smb1-pins { 890 groups = "smb1"; 891 function = "smb1"; 892 }; 893 smb2_pins: smb2-pins { 894 groups = "smb2"; 895 function = "smb2"; 896 }; 897 smb2c_pins: smb2c-pins { 898 groups = "smb2c"; 899 function = "smb2c"; 900 }; 901 smb2b_pins: smb2b-pins { 902 groups = "smb2b"; 903 function = "smb2b"; 904 }; 905 smb1c_pins: smb1c-pins { 906 groups = "smb1c"; 907 function = "smb1c"; 908 }; 909 smb1b_pins: smb1b-pins { 910 groups = "smb1b"; 911 function = "smb1b"; 912 }; 913 smb8_pins: smb8-pins { 914 groups = "smb8"; 915 function = "smb8"; 916 }; 917 smb9_pins: smb9-pins { 918 groups = "smb9"; 919 function = "smb9"; 920 }; 921 smb10_pins: smb10-pins { 922 groups = "smb10"; 923 function = "smb10"; 924 }; 925 smb11_pins: smb11-pins { 926 groups = "smb11"; 927 function = "smb11"; 928 }; 929 sd1_pins: sd1-pins { 930 groups = "sd1"; 931 function = "sd1"; 932 }; 933 sd1pwr_pins: sd1pwr-pins { 934 groups = "sd1pwr"; 935 function = "sd1pwr"; 936 }; 937 pwm4_pins: pwm4-pins { 938 groups = "pwm4"; 939 function = "pwm4"; 940 }; 941 pwm5_pins: pwm5-pins { 942 groups = "pwm5"; 943 function = "pwm5"; 944 }; 945 pwm6_pins: pwm6-pins { 946 groups = "pwm6"; 947 function = "pwm6"; 948 }; 949 pwm7_pins: pwm7-pins { 950 groups = "pwm7"; 951 function = "pwm7"; 952 }; 953 mmc8_pins: mmc8-pins { 954 groups = "mmc8"; 955 function = "mmc8"; 956 }; 957 mmc_pins: mmc-pins { 958 groups = "mmc"; 959 function = "mmc"; 960 }; 961 mmcwp_pins: mmcwp-pins { 962 groups = "mmcwp"; 963 function = "mmcwp"; 964 }; 965 mmccd_pins: mmccd-pins { 966 groups = "mmccd"; 967 function = "mmccd"; 968 }; 969 mmcrst_pins: mmcrst-pins { 970 groups = "mmcrst"; 971 function = "mmcrst"; 972 }; 973 clkout_pins: clkout-pins { 974 groups = "clkout"; 975 function = "clkout"; 976 }; 977 serirq_pins: serirq-pins { 978 groups = "serirq"; 979 function = "serirq"; 980 }; 981 lpcclk_pins: lpcclk-pins { 982 groups = "lpcclk"; 983 function = "lpcclk"; 984 }; 985 scipme_pins: scipme-pins { 986 groups = "scipme"; 987 function = "scipme"; 988 }; 989 sci_pins: sci-pins { 990 groups = "sci"; 991 function = "sci"; 992 }; 993 smb6_pins: smb6-pins { 994 groups = "smb6"; 995 function = "smb6"; 996 }; 997 smb7_pins: smb7-pins { 998 groups = "smb7"; 999 function = "smb7"; 1000 }; 1001 pspi1_pins: pspi1-pins { 1002 groups = "pspi1"; 1003 function = "pspi1"; 1004 }; 1005 faninx_pins: faninx-pins { 1006 groups = "faninx"; 1007 function = "faninx"; 1008 }; 1009 r1_pins: r1-pins { 1010 groups = "r1"; 1011 function = "r1"; 1012 }; 1013 spi3_pins: spi3-pins { 1014 groups = "spi3"; 1015 function = "spi3"; 1016 }; 1017 spi3cs1_pins: spi3cs1-pins { 1018 groups = "spi3cs1"; 1019 function = "spi3cs1"; 1020 }; 1021 spi3quad_pins: spi3quad-pins { 1022 groups = "spi3quad"; 1023 function = "spi3quad"; 1024 }; 1025 spi3cs2_pins: spi3cs2-pins { 1026 groups = "spi3cs2"; 1027 function = "spi3cs2"; 1028 }; 1029 spi3cs3_pins: spi3cs3-pins { 1030 groups = "spi3cs3"; 1031 function = "spi3cs3"; 1032 }; 1033 nprd_smi_pins: nprd-smi-pins { 1034 groups = "nprd_smi"; 1035 function = "nprd_smi"; 1036 }; 1037 smb0b_pins: smb0b-pins { 1038 groups = "smb0b"; 1039 function = "smb0b"; 1040 }; 1041 smb0c_pins: smb0c-pins { 1042 groups = "smb0c"; 1043 function = "smb0c"; 1044 }; 1045 smb0den_pins: smb0den-pins { 1046 groups = "smb0den"; 1047 function = "smb0den"; 1048 }; 1049 smb0d_pins: smb0d-pins { 1050 groups = "smb0d"; 1051 function = "smb0d"; 1052 }; 1053 ddc_pins: ddc-pins { 1054 groups = "ddc"; 1055 function = "ddc"; 1056 }; 1057 rg2mdio_pins: rg2mdio-pins { 1058 groups = "rg2mdio"; 1059 function = "rg2mdio"; 1060 }; 1061 wdog1_pins: wdog1-pins { 1062 groups = "wdog1"; 1063 function = "wdog1"; 1064 }; 1065 wdog2_pins: wdog2-pins { 1066 groups = "wdog2"; 1067 function = "wdog2"; 1068 }; 1069 smb12_pins: smb12-pins { 1070 groups = "smb12"; 1071 function = "smb12"; 1072 }; 1073 smb13_pins: smb13-pins { 1074 groups = "smb13"; 1075 function = "smb13"; 1076 }; 1077 spix_pins: spix-pins { 1078 groups = "spix"; 1079 function = "spix"; 1080 }; 1081 spixcs1_pins: spixcs1-pins { 1082 groups = "spixcs1"; 1083 function = "spixcs1"; 1084 }; 1085 clkreq_pins: clkreq-pins { 1086 groups = "clkreq"; 1087 function = "clkreq"; 1088 }; 1089 hgpio0_pins: hgpio0-pins { 1090 groups = "hgpio0"; 1091 function = "hgpio0"; 1092 }; 1093 hgpio1_pins: hgpio1-pins { 1094 groups = "hgpio1"; 1095 function = "hgpio1"; 1096 }; 1097 hgpio2_pins: hgpio2-pins { 1098 groups = "hgpio2"; 1099 function = "hgpio2"; 1100 }; 1101 hgpio3_pins: hgpio3-pins { 1102 groups = "hgpio3"; 1103 function = "hgpio3"; 1104 }; 1105 hgpio4_pins: hgpio4-pins { 1106 groups = "hgpio4"; 1107 function = "hgpio4"; 1108 }; 1109 hgpio5_pins: hgpio5-pins { 1110 groups = "hgpio5"; 1111 function = "hgpio5"; 1112 }; 1113 hgpio6_pins: hgpio6-pins { 1114 groups = "hgpio6"; 1115 function = "hgpio6"; 1116 }; 1117 hgpio7_pins: hgpio7-pins { 1118 groups = "hgpio7"; 1119 function = "hgpio7"; 1120 }; 1121 }; 1122};