cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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omap24xx-clocks.dtsi (26252B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Device Tree Source for OMAP24xx clock data
      4 *
      5 * Copyright (C) 2014 Texas Instruments, Inc.
      6 */
      7&scm_clocks {
      8	mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
      9		#clock-cells = <0>;
     10		compatible = "ti,composite-mux-clock";
     11		clocks = <&func_96m_ck>, <&mcbsp_clks>;
     12		ti,bit-shift = <2>;
     13		reg = <0x4>;
     14	};
     15
     16	mcbsp1_fck: mcbsp1_fck {
     17		#clock-cells = <0>;
     18		compatible = "ti,composite-clock";
     19		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
     20	};
     21
     22	mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
     23		#clock-cells = <0>;
     24		compatible = "ti,composite-mux-clock";
     25		clocks = <&func_96m_ck>, <&mcbsp_clks>;
     26		ti,bit-shift = <6>;
     27		reg = <0x4>;
     28	};
     29
     30	mcbsp2_fck: mcbsp2_fck {
     31		#clock-cells = <0>;
     32		compatible = "ti,composite-clock";
     33		clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
     34	};
     35};
     36
     37&prcm_clocks {
     38	func_32k_ck: func_32k_ck {
     39		#clock-cells = <0>;
     40		compatible = "fixed-clock";
     41		clock-frequency = <32768>;
     42	};
     43
     44	secure_32k_ck: secure_32k_ck {
     45		#clock-cells = <0>;
     46		compatible = "fixed-clock";
     47		clock-frequency = <32768>;
     48	};
     49
     50	virt_12m_ck: virt_12m_ck {
     51		#clock-cells = <0>;
     52		compatible = "fixed-clock";
     53		clock-frequency = <12000000>;
     54	};
     55
     56	virt_13m_ck: virt_13m_ck {
     57		#clock-cells = <0>;
     58		compatible = "fixed-clock";
     59		clock-frequency = <13000000>;
     60	};
     61
     62	virt_19200000_ck: virt_19200000_ck {
     63		#clock-cells = <0>;
     64		compatible = "fixed-clock";
     65		clock-frequency = <19200000>;
     66	};
     67
     68	virt_26m_ck: virt_26m_ck {
     69		#clock-cells = <0>;
     70		compatible = "fixed-clock";
     71		clock-frequency = <26000000>;
     72	};
     73
     74	aplls_clkin_ck: aplls_clkin_ck@540 {
     75		#clock-cells = <0>;
     76		compatible = "ti,mux-clock";
     77		clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
     78		ti,bit-shift = <23>;
     79		reg = <0x0540>;
     80	};
     81
     82	aplls_clkin_x2_ck: aplls_clkin_x2_ck {
     83		#clock-cells = <0>;
     84		compatible = "fixed-factor-clock";
     85		clocks = <&aplls_clkin_ck>;
     86		clock-mult = <2>;
     87		clock-div = <1>;
     88	};
     89
     90	osc_ck: osc_ck@60 {
     91		#clock-cells = <0>;
     92		compatible = "ti,mux-clock";
     93		clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
     94		ti,bit-shift = <6>;
     95		reg = <0x0060>;
     96		ti,index-starts-at-one;
     97	};
     98
     99	sys_ck: sys_ck@60 {
    100		#clock-cells = <0>;
    101		compatible = "ti,divider-clock";
    102		clocks = <&osc_ck>;
    103		ti,bit-shift = <6>;
    104		ti,max-div = <3>;
    105		reg = <0x0060>;
    106		ti,index-starts-at-one;
    107	};
    108
    109	alt_ck: alt_ck {
    110		#clock-cells = <0>;
    111		compatible = "fixed-clock";
    112		clock-frequency = <54000000>;
    113	};
    114
    115	mcbsp_clks: mcbsp_clks {
    116		#clock-cells = <0>;
    117		compatible = "fixed-clock";
    118		clock-frequency = <0x0>;
    119	};
    120
    121	dpll_ck: dpll_ck@500 {
    122		#clock-cells = <0>;
    123		compatible = "ti,omap2-dpll-core-clock";
    124		clocks = <&sys_ck>, <&sys_ck>;
    125		reg = <0x0500>, <0x0540>;
    126	};
    127
    128	apll96_ck: apll96_ck@500 {
    129		#clock-cells = <0>;
    130		compatible = "ti,omap2-apll-clock";
    131		clocks = <&sys_ck>;
    132		ti,bit-shift = <2>;
    133		ti,idlest-shift = <8>;
    134		ti,clock-frequency = <96000000>;
    135		reg = <0x0500>, <0x0530>, <0x0520>;
    136	};
    137
    138	apll54_ck: apll54_ck@500 {
    139		#clock-cells = <0>;
    140		compatible = "ti,omap2-apll-clock";
    141		clocks = <&sys_ck>;
    142		ti,bit-shift = <6>;
    143		ti,idlest-shift = <9>;
    144		ti,clock-frequency = <54000000>;
    145		reg = <0x0500>, <0x0530>, <0x0520>;
    146	};
    147
    148	func_54m_ck: func_54m_ck@540 {
    149		#clock-cells = <0>;
    150		compatible = "ti,mux-clock";
    151		clocks = <&apll54_ck>, <&alt_ck>;
    152		ti,bit-shift = <5>;
    153		reg = <0x0540>;
    154	};
    155
    156	core_ck: core_ck {
    157		#clock-cells = <0>;
    158		compatible = "fixed-factor-clock";
    159		clocks = <&dpll_ck>;
    160		clock-mult = <1>;
    161		clock-div = <1>;
    162	};
    163
    164	func_96m_ck: func_96m_ck@540 {
    165		#clock-cells = <0>;
    166	};
    167
    168	apll96_d2_ck: apll96_d2_ck {
    169		#clock-cells = <0>;
    170		compatible = "fixed-factor-clock";
    171		clocks = <&apll96_ck>;
    172		clock-mult = <1>;
    173		clock-div = <2>;
    174	};
    175
    176	func_48m_ck: func_48m_ck@540 {
    177		#clock-cells = <0>;
    178		compatible = "ti,mux-clock";
    179		clocks = <&apll96_d2_ck>, <&alt_ck>;
    180		ti,bit-shift = <3>;
    181		reg = <0x0540>;
    182	};
    183
    184	func_12m_ck: func_12m_ck {
    185		#clock-cells = <0>;
    186		compatible = "fixed-factor-clock";
    187		clocks = <&func_48m_ck>;
    188		clock-mult = <1>;
    189		clock-div = <4>;
    190	};
    191
    192	sys_clkout_src_gate: sys_clkout_src_gate@70 {
    193		#clock-cells = <0>;
    194		compatible = "ti,composite-no-wait-gate-clock";
    195		clocks = <&core_ck>;
    196		ti,bit-shift = <7>;
    197		reg = <0x0070>;
    198	};
    199
    200	sys_clkout_src_mux: sys_clkout_src_mux@70 {
    201		#clock-cells = <0>;
    202		compatible = "ti,composite-mux-clock";
    203		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
    204		reg = <0x0070>;
    205	};
    206
    207	sys_clkout_src: sys_clkout_src {
    208		#clock-cells = <0>;
    209		compatible = "ti,composite-clock";
    210		clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
    211	};
    212
    213	sys_clkout: sys_clkout@70 {
    214		#clock-cells = <0>;
    215		compatible = "ti,divider-clock";
    216		clocks = <&sys_clkout_src>;
    217		ti,bit-shift = <3>;
    218		ti,max-div = <64>;
    219		reg = <0x0070>;
    220		ti,index-power-of-two;
    221	};
    222
    223	emul_ck: emul_ck@78 {
    224		#clock-cells = <0>;
    225		compatible = "ti,gate-clock";
    226		clocks = <&func_54m_ck>;
    227		ti,bit-shift = <0>;
    228		reg = <0x0078>;
    229	};
    230
    231	mpu_ck: mpu_ck@140 {
    232		#clock-cells = <0>;
    233		compatible = "ti,divider-clock";
    234		clocks = <&core_ck>;
    235		ti,max-div = <31>;
    236		reg = <0x0140>;
    237		ti,index-starts-at-one;
    238	};
    239
    240	dsp_gate_fck: dsp_gate_fck@800 {
    241		#clock-cells = <0>;
    242		compatible = "ti,composite-gate-clock";
    243		clocks = <&core_ck>;
    244		ti,bit-shift = <0>;
    245		reg = <0x0800>;
    246	};
    247
    248	dsp_div_fck: dsp_div_fck@840 {
    249		#clock-cells = <0>;
    250		compatible = "ti,composite-divider-clock";
    251		clocks = <&core_ck>;
    252		reg = <0x0840>;
    253	};
    254
    255	dsp_fck: dsp_fck {
    256		#clock-cells = <0>;
    257		compatible = "ti,composite-clock";
    258		clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
    259	};
    260
    261	core_l3_ck: core_l3_ck@240 {
    262		#clock-cells = <0>;
    263		compatible = "ti,divider-clock";
    264		clocks = <&core_ck>;
    265		ti,max-div = <31>;
    266		reg = <0x0240>;
    267		ti,index-starts-at-one;
    268	};
    269
    270	gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
    271		#clock-cells = <0>;
    272		compatible = "ti,composite-gate-clock";
    273		clocks = <&core_l3_ck>;
    274		ti,bit-shift = <2>;
    275		reg = <0x0300>;
    276	};
    277
    278	gfx_3d_div_fck: gfx_3d_div_fck@340 {
    279		#clock-cells = <0>;
    280		compatible = "ti,composite-divider-clock";
    281		clocks = <&core_l3_ck>;
    282		ti,max-div = <4>;
    283		reg = <0x0340>;
    284		ti,index-starts-at-one;
    285	};
    286
    287	gfx_3d_fck: gfx_3d_fck {
    288		#clock-cells = <0>;
    289		compatible = "ti,composite-clock";
    290		clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
    291	};
    292
    293	gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
    294		#clock-cells = <0>;
    295		compatible = "ti,composite-gate-clock";
    296		clocks = <&core_l3_ck>;
    297		ti,bit-shift = <1>;
    298		reg = <0x0300>;
    299	};
    300
    301	gfx_2d_div_fck: gfx_2d_div_fck@340 {
    302		#clock-cells = <0>;
    303		compatible = "ti,composite-divider-clock";
    304		clocks = <&core_l3_ck>;
    305		ti,max-div = <4>;
    306		reg = <0x0340>;
    307		ti,index-starts-at-one;
    308	};
    309
    310	gfx_2d_fck: gfx_2d_fck {
    311		#clock-cells = <0>;
    312		compatible = "ti,composite-clock";
    313		clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
    314	};
    315
    316	gfx_ick: gfx_ick@310 {
    317		#clock-cells = <0>;
    318		compatible = "ti,wait-gate-clock";
    319		clocks = <&core_l3_ck>;
    320		ti,bit-shift = <0>;
    321		reg = <0x0310>;
    322	};
    323
    324	l4_ck: l4_ck@240 {
    325		#clock-cells = <0>;
    326		compatible = "ti,divider-clock";
    327		clocks = <&core_l3_ck>;
    328		ti,bit-shift = <5>;
    329		ti,max-div = <3>;
    330		reg = <0x0240>;
    331		ti,index-starts-at-one;
    332	};
    333
    334	dss_ick: dss_ick@210 {
    335		#clock-cells = <0>;
    336		compatible = "ti,omap3-no-wait-interface-clock";
    337		clocks = <&l4_ck>;
    338		ti,bit-shift = <0>;
    339		reg = <0x0210>;
    340	};
    341
    342	dss1_gate_fck: dss1_gate_fck@200 {
    343		#clock-cells = <0>;
    344		compatible = "ti,composite-no-wait-gate-clock";
    345		clocks = <&core_ck>;
    346		ti,bit-shift = <0>;
    347		reg = <0x0200>;
    348	};
    349
    350	core_d2_ck: core_d2_ck {
    351		#clock-cells = <0>;
    352		compatible = "fixed-factor-clock";
    353		clocks = <&core_ck>;
    354		clock-mult = <1>;
    355		clock-div = <2>;
    356	};
    357
    358	core_d3_ck: core_d3_ck {
    359		#clock-cells = <0>;
    360		compatible = "fixed-factor-clock";
    361		clocks = <&core_ck>;
    362		clock-mult = <1>;
    363		clock-div = <3>;
    364	};
    365
    366	core_d4_ck: core_d4_ck {
    367		#clock-cells = <0>;
    368		compatible = "fixed-factor-clock";
    369		clocks = <&core_ck>;
    370		clock-mult = <1>;
    371		clock-div = <4>;
    372	};
    373
    374	core_d5_ck: core_d5_ck {
    375		#clock-cells = <0>;
    376		compatible = "fixed-factor-clock";
    377		clocks = <&core_ck>;
    378		clock-mult = <1>;
    379		clock-div = <5>;
    380	};
    381
    382	core_d6_ck: core_d6_ck {
    383		#clock-cells = <0>;
    384		compatible = "fixed-factor-clock";
    385		clocks = <&core_ck>;
    386		clock-mult = <1>;
    387		clock-div = <6>;
    388	};
    389
    390	dummy_ck: dummy_ck {
    391		#clock-cells = <0>;
    392		compatible = "fixed-clock";
    393		clock-frequency = <0>;
    394	};
    395
    396	core_d8_ck: core_d8_ck {
    397		#clock-cells = <0>;
    398		compatible = "fixed-factor-clock";
    399		clocks = <&core_ck>;
    400		clock-mult = <1>;
    401		clock-div = <8>;
    402	};
    403
    404	core_d9_ck: core_d9_ck {
    405		#clock-cells = <0>;
    406		compatible = "fixed-factor-clock";
    407		clocks = <&core_ck>;
    408		clock-mult = <1>;
    409		clock-div = <9>;
    410	};
    411
    412	core_d12_ck: core_d12_ck {
    413		#clock-cells = <0>;
    414		compatible = "fixed-factor-clock";
    415		clocks = <&core_ck>;
    416		clock-mult = <1>;
    417		clock-div = <12>;
    418	};
    419
    420	core_d16_ck: core_d16_ck {
    421		#clock-cells = <0>;
    422		compatible = "fixed-factor-clock";
    423		clocks = <&core_ck>;
    424		clock-mult = <1>;
    425		clock-div = <16>;
    426	};
    427
    428	dss1_mux_fck: dss1_mux_fck@240 {
    429		#clock-cells = <0>;
    430		compatible = "ti,composite-mux-clock";
    431		clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
    432		ti,bit-shift = <8>;
    433		reg = <0x0240>;
    434	};
    435
    436	dss1_fck: dss1_fck {
    437		#clock-cells = <0>;
    438		compatible = "ti,composite-clock";
    439		clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
    440	};
    441
    442	dss2_gate_fck: dss2_gate_fck@200 {
    443		#clock-cells = <0>;
    444		compatible = "ti,composite-no-wait-gate-clock";
    445		clocks = <&func_48m_ck>;
    446		ti,bit-shift = <1>;
    447		reg = <0x0200>;
    448	};
    449
    450	dss2_mux_fck: dss2_mux_fck@240 {
    451		#clock-cells = <0>;
    452		compatible = "ti,composite-mux-clock";
    453		clocks = <&sys_ck>, <&func_48m_ck>;
    454		ti,bit-shift = <13>;
    455		reg = <0x0240>;
    456	};
    457
    458	dss2_fck: dss2_fck {
    459		#clock-cells = <0>;
    460		compatible = "ti,composite-clock";
    461		clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
    462	};
    463
    464	dss_54m_fck: dss_54m_fck@200 {
    465		#clock-cells = <0>;
    466		compatible = "ti,wait-gate-clock";
    467		clocks = <&func_54m_ck>;
    468		ti,bit-shift = <2>;
    469		reg = <0x0200>;
    470	};
    471
    472	ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
    473		#clock-cells = <0>;
    474		compatible = "ti,composite-gate-clock";
    475		clocks = <&core_ck>;
    476		ti,bit-shift = <1>;
    477		reg = <0x0204>;
    478	};
    479
    480	ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
    481		#clock-cells = <0>;
    482		compatible = "ti,composite-divider-clock";
    483		clocks = <&core_ck>;
    484		ti,bit-shift = <20>;
    485		reg = <0x0240>;
    486	};
    487
    488	ssi_ssr_sst_fck: ssi_ssr_sst_fck {
    489		#clock-cells = <0>;
    490		compatible = "ti,composite-clock";
    491		clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
    492	};
    493
    494	usb_l4_gate_ick: usb_l4_gate_ick@214 {
    495		#clock-cells = <0>;
    496		compatible = "ti,composite-interface-clock";
    497		clocks = <&core_l3_ck>;
    498		ti,bit-shift = <0>;
    499		reg = <0x0214>;
    500	};
    501
    502	usb_l4_div_ick: usb_l4_div_ick@240 {
    503		#clock-cells = <0>;
    504		compatible = "ti,composite-divider-clock";
    505		clocks = <&core_l3_ck>;
    506		ti,bit-shift = <25>;
    507		reg = <0x0240>;
    508		ti,dividers = <0>, <1>, <2>, <0>, <4>;
    509	};
    510
    511	usb_l4_ick: usb_l4_ick {
    512		#clock-cells = <0>;
    513		compatible = "ti,composite-clock";
    514		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
    515	};
    516
    517	ssi_l4_ick: ssi_l4_ick@214 {
    518		#clock-cells = <0>;
    519		compatible = "ti,omap3-interface-clock";
    520		clocks = <&l4_ck>;
    521		ti,bit-shift = <1>;
    522		reg = <0x0214>;
    523	};
    524
    525	gpt1_ick: gpt1_ick@410 {
    526		#clock-cells = <0>;
    527		compatible = "ti,omap3-interface-clock";
    528		clocks = <&sys_ck>;
    529		ti,bit-shift = <0>;
    530		reg = <0x0410>;
    531	};
    532
    533	gpt1_gate_fck: gpt1_gate_fck@400 {
    534		#clock-cells = <0>;
    535		compatible = "ti,composite-gate-clock";
    536		clocks = <&func_32k_ck>;
    537		ti,bit-shift = <0>;
    538		reg = <0x0400>;
    539	};
    540
    541	gpt1_mux_fck: gpt1_mux_fck@440 {
    542		#clock-cells = <0>;
    543		compatible = "ti,composite-mux-clock";
    544		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    545		reg = <0x0440>;
    546	};
    547
    548	gpt1_fck: gpt1_fck {
    549		#clock-cells = <0>;
    550		compatible = "ti,composite-clock";
    551		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
    552	};
    553
    554	gpt2_ick: gpt2_ick@210 {
    555		#clock-cells = <0>;
    556		compatible = "ti,omap3-interface-clock";
    557		clocks = <&l4_ck>;
    558		ti,bit-shift = <4>;
    559		reg = <0x0210>;
    560	};
    561
    562	gpt2_gate_fck: gpt2_gate_fck@200 {
    563		#clock-cells = <0>;
    564		compatible = "ti,composite-gate-clock";
    565		clocks = <&func_32k_ck>;
    566		ti,bit-shift = <4>;
    567		reg = <0x0200>;
    568	};
    569
    570	gpt2_mux_fck: gpt2_mux_fck@244 {
    571		#clock-cells = <0>;
    572		compatible = "ti,composite-mux-clock";
    573		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    574		ti,bit-shift = <2>;
    575		reg = <0x0244>;
    576	};
    577
    578	gpt2_fck: gpt2_fck {
    579		#clock-cells = <0>;
    580		compatible = "ti,composite-clock";
    581		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
    582	};
    583
    584	gpt3_ick: gpt3_ick@210 {
    585		#clock-cells = <0>;
    586		compatible = "ti,omap3-interface-clock";
    587		clocks = <&l4_ck>;
    588		ti,bit-shift = <5>;
    589		reg = <0x0210>;
    590	};
    591
    592	gpt3_gate_fck: gpt3_gate_fck@200 {
    593		#clock-cells = <0>;
    594		compatible = "ti,composite-gate-clock";
    595		clocks = <&func_32k_ck>;
    596		ti,bit-shift = <5>;
    597		reg = <0x0200>;
    598	};
    599
    600	gpt3_mux_fck: gpt3_mux_fck@244 {
    601		#clock-cells = <0>;
    602		compatible = "ti,composite-mux-clock";
    603		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    604		ti,bit-shift = <4>;
    605		reg = <0x0244>;
    606	};
    607
    608	gpt3_fck: gpt3_fck {
    609		#clock-cells = <0>;
    610		compatible = "ti,composite-clock";
    611		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
    612	};
    613
    614	gpt4_ick: gpt4_ick@210 {
    615		#clock-cells = <0>;
    616		compatible = "ti,omap3-interface-clock";
    617		clocks = <&l4_ck>;
    618		ti,bit-shift = <6>;
    619		reg = <0x0210>;
    620	};
    621
    622	gpt4_gate_fck: gpt4_gate_fck@200 {
    623		#clock-cells = <0>;
    624		compatible = "ti,composite-gate-clock";
    625		clocks = <&func_32k_ck>;
    626		ti,bit-shift = <6>;
    627		reg = <0x0200>;
    628	};
    629
    630	gpt4_mux_fck: gpt4_mux_fck@244 {
    631		#clock-cells = <0>;
    632		compatible = "ti,composite-mux-clock";
    633		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    634		ti,bit-shift = <6>;
    635		reg = <0x0244>;
    636	};
    637
    638	gpt4_fck: gpt4_fck {
    639		#clock-cells = <0>;
    640		compatible = "ti,composite-clock";
    641		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
    642	};
    643
    644	gpt5_ick: gpt5_ick@210 {
    645		#clock-cells = <0>;
    646		compatible = "ti,omap3-interface-clock";
    647		clocks = <&l4_ck>;
    648		ti,bit-shift = <7>;
    649		reg = <0x0210>;
    650	};
    651
    652	gpt5_gate_fck: gpt5_gate_fck@200 {
    653		#clock-cells = <0>;
    654		compatible = "ti,composite-gate-clock";
    655		clocks = <&func_32k_ck>;
    656		ti,bit-shift = <7>;
    657		reg = <0x0200>;
    658	};
    659
    660	gpt5_mux_fck: gpt5_mux_fck@244 {
    661		#clock-cells = <0>;
    662		compatible = "ti,composite-mux-clock";
    663		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    664		ti,bit-shift = <8>;
    665		reg = <0x0244>;
    666	};
    667
    668	gpt5_fck: gpt5_fck {
    669		#clock-cells = <0>;
    670		compatible = "ti,composite-clock";
    671		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
    672	};
    673
    674	gpt6_ick: gpt6_ick@210 {
    675		#clock-cells = <0>;
    676		compatible = "ti,omap3-interface-clock";
    677		clocks = <&l4_ck>;
    678		ti,bit-shift = <8>;
    679		reg = <0x0210>;
    680	};
    681
    682	gpt6_gate_fck: gpt6_gate_fck@200 {
    683		#clock-cells = <0>;
    684		compatible = "ti,composite-gate-clock";
    685		clocks = <&func_32k_ck>;
    686		ti,bit-shift = <8>;
    687		reg = <0x0200>;
    688	};
    689
    690	gpt6_mux_fck: gpt6_mux_fck@244 {
    691		#clock-cells = <0>;
    692		compatible = "ti,composite-mux-clock";
    693		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    694		ti,bit-shift = <10>;
    695		reg = <0x0244>;
    696	};
    697
    698	gpt6_fck: gpt6_fck {
    699		#clock-cells = <0>;
    700		compatible = "ti,composite-clock";
    701		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
    702	};
    703
    704	gpt7_ick: gpt7_ick@210 {
    705		#clock-cells = <0>;
    706		compatible = "ti,omap3-interface-clock";
    707		clocks = <&l4_ck>;
    708		ti,bit-shift = <9>;
    709		reg = <0x0210>;
    710	};
    711
    712	gpt7_gate_fck: gpt7_gate_fck@200 {
    713		#clock-cells = <0>;
    714		compatible = "ti,composite-gate-clock";
    715		clocks = <&func_32k_ck>;
    716		ti,bit-shift = <9>;
    717		reg = <0x0200>;
    718	};
    719
    720	gpt7_mux_fck: gpt7_mux_fck@244 {
    721		#clock-cells = <0>;
    722		compatible = "ti,composite-mux-clock";
    723		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    724		ti,bit-shift = <12>;
    725		reg = <0x0244>;
    726	};
    727
    728	gpt7_fck: gpt7_fck {
    729		#clock-cells = <0>;
    730		compatible = "ti,composite-clock";
    731		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
    732	};
    733
    734	gpt8_ick: gpt8_ick@210 {
    735		#clock-cells = <0>;
    736		compatible = "ti,omap3-interface-clock";
    737		clocks = <&l4_ck>;
    738		ti,bit-shift = <10>;
    739		reg = <0x0210>;
    740	};
    741
    742	gpt8_gate_fck: gpt8_gate_fck@200 {
    743		#clock-cells = <0>;
    744		compatible = "ti,composite-gate-clock";
    745		clocks = <&func_32k_ck>;
    746		ti,bit-shift = <10>;
    747		reg = <0x0200>;
    748	};
    749
    750	gpt8_mux_fck: gpt8_mux_fck@244 {
    751		#clock-cells = <0>;
    752		compatible = "ti,composite-mux-clock";
    753		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    754		ti,bit-shift = <14>;
    755		reg = <0x0244>;
    756	};
    757
    758	gpt8_fck: gpt8_fck {
    759		#clock-cells = <0>;
    760		compatible = "ti,composite-clock";
    761		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
    762	};
    763
    764	gpt9_ick: gpt9_ick@210 {
    765		#clock-cells = <0>;
    766		compatible = "ti,omap3-interface-clock";
    767		clocks = <&l4_ck>;
    768		ti,bit-shift = <11>;
    769		reg = <0x0210>;
    770	};
    771
    772	gpt9_gate_fck: gpt9_gate_fck@200 {
    773		#clock-cells = <0>;
    774		compatible = "ti,composite-gate-clock";
    775		clocks = <&func_32k_ck>;
    776		ti,bit-shift = <11>;
    777		reg = <0x0200>;
    778	};
    779
    780	gpt9_mux_fck: gpt9_mux_fck@244 {
    781		#clock-cells = <0>;
    782		compatible = "ti,composite-mux-clock";
    783		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    784		ti,bit-shift = <16>;
    785		reg = <0x0244>;
    786	};
    787
    788	gpt9_fck: gpt9_fck {
    789		#clock-cells = <0>;
    790		compatible = "ti,composite-clock";
    791		clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
    792	};
    793
    794	gpt10_ick: gpt10_ick@210 {
    795		#clock-cells = <0>;
    796		compatible = "ti,omap3-interface-clock";
    797		clocks = <&l4_ck>;
    798		ti,bit-shift = <12>;
    799		reg = <0x0210>;
    800	};
    801
    802	gpt10_gate_fck: gpt10_gate_fck@200 {
    803		#clock-cells = <0>;
    804		compatible = "ti,composite-gate-clock";
    805		clocks = <&func_32k_ck>;
    806		ti,bit-shift = <12>;
    807		reg = <0x0200>;
    808	};
    809
    810	gpt10_mux_fck: gpt10_mux_fck@244 {
    811		#clock-cells = <0>;
    812		compatible = "ti,composite-mux-clock";
    813		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    814		ti,bit-shift = <18>;
    815		reg = <0x0244>;
    816	};
    817
    818	gpt10_fck: gpt10_fck {
    819		#clock-cells = <0>;
    820		compatible = "ti,composite-clock";
    821		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
    822	};
    823
    824	gpt11_ick: gpt11_ick@210 {
    825		#clock-cells = <0>;
    826		compatible = "ti,omap3-interface-clock";
    827		clocks = <&l4_ck>;
    828		ti,bit-shift = <13>;
    829		reg = <0x0210>;
    830	};
    831
    832	gpt11_gate_fck: gpt11_gate_fck@200 {
    833		#clock-cells = <0>;
    834		compatible = "ti,composite-gate-clock";
    835		clocks = <&func_32k_ck>;
    836		ti,bit-shift = <13>;
    837		reg = <0x0200>;
    838	};
    839
    840	gpt11_mux_fck: gpt11_mux_fck@244 {
    841		#clock-cells = <0>;
    842		compatible = "ti,composite-mux-clock";
    843		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    844		ti,bit-shift = <20>;
    845		reg = <0x0244>;
    846	};
    847
    848	gpt11_fck: gpt11_fck {
    849		#clock-cells = <0>;
    850		compatible = "ti,composite-clock";
    851		clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
    852	};
    853
    854	gpt12_ick: gpt12_ick@210 {
    855		#clock-cells = <0>;
    856		compatible = "ti,omap3-interface-clock";
    857		clocks = <&l4_ck>;
    858		ti,bit-shift = <14>;
    859		reg = <0x0210>;
    860	};
    861
    862	gpt12_gate_fck: gpt12_gate_fck@200 {
    863		#clock-cells = <0>;
    864		compatible = "ti,composite-gate-clock";
    865		clocks = <&func_32k_ck>;
    866		ti,bit-shift = <14>;
    867		reg = <0x0200>;
    868	};
    869
    870	gpt12_mux_fck: gpt12_mux_fck@244 {
    871		#clock-cells = <0>;
    872		compatible = "ti,composite-mux-clock";
    873		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
    874		ti,bit-shift = <22>;
    875		reg = <0x0244>;
    876	};
    877
    878	gpt12_fck: gpt12_fck {
    879		#clock-cells = <0>;
    880		compatible = "ti,composite-clock";
    881		clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
    882	};
    883
    884	mcbsp1_ick: mcbsp1_ick@210 {
    885		#clock-cells = <0>;
    886		compatible = "ti,omap3-interface-clock";
    887		clocks = <&l4_ck>;
    888		ti,bit-shift = <15>;
    889		reg = <0x0210>;
    890	};
    891
    892	mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
    893		#clock-cells = <0>;
    894		compatible = "ti,composite-gate-clock";
    895		clocks = <&mcbsp_clks>;
    896		ti,bit-shift = <15>;
    897		reg = <0x0200>;
    898	};
    899
    900	mcbsp2_ick: mcbsp2_ick@210 {
    901		#clock-cells = <0>;
    902		compatible = "ti,omap3-interface-clock";
    903		clocks = <&l4_ck>;
    904		ti,bit-shift = <16>;
    905		reg = <0x0210>;
    906	};
    907
    908	mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
    909		#clock-cells = <0>;
    910		compatible = "ti,composite-gate-clock";
    911		clocks = <&mcbsp_clks>;
    912		ti,bit-shift = <16>;
    913		reg = <0x0200>;
    914	};
    915
    916	mcspi1_ick: mcspi1_ick@210 {
    917		#clock-cells = <0>;
    918		compatible = "ti,omap3-interface-clock";
    919		clocks = <&l4_ck>;
    920		ti,bit-shift = <17>;
    921		reg = <0x0210>;
    922	};
    923
    924	mcspi1_fck: mcspi1_fck@200 {
    925		#clock-cells = <0>;
    926		compatible = "ti,wait-gate-clock";
    927		clocks = <&func_48m_ck>;
    928		ti,bit-shift = <17>;
    929		reg = <0x0200>;
    930	};
    931
    932	mcspi2_ick: mcspi2_ick@210 {
    933		#clock-cells = <0>;
    934		compatible = "ti,omap3-interface-clock";
    935		clocks = <&l4_ck>;
    936		ti,bit-shift = <18>;
    937		reg = <0x0210>;
    938	};
    939
    940	mcspi2_fck: mcspi2_fck@200 {
    941		#clock-cells = <0>;
    942		compatible = "ti,wait-gate-clock";
    943		clocks = <&func_48m_ck>;
    944		ti,bit-shift = <18>;
    945		reg = <0x0200>;
    946	};
    947
    948	uart1_ick: uart1_ick@210 {
    949		#clock-cells = <0>;
    950		compatible = "ti,omap3-interface-clock";
    951		clocks = <&l4_ck>;
    952		ti,bit-shift = <21>;
    953		reg = <0x0210>;
    954	};
    955
    956	uart1_fck: uart1_fck@200 {
    957		#clock-cells = <0>;
    958		compatible = "ti,wait-gate-clock";
    959		clocks = <&func_48m_ck>;
    960		ti,bit-shift = <21>;
    961		reg = <0x0200>;
    962	};
    963
    964	uart2_ick: uart2_ick@210 {
    965		#clock-cells = <0>;
    966		compatible = "ti,omap3-interface-clock";
    967		clocks = <&l4_ck>;
    968		ti,bit-shift = <22>;
    969		reg = <0x0210>;
    970	};
    971
    972	uart2_fck: uart2_fck@200 {
    973		#clock-cells = <0>;
    974		compatible = "ti,wait-gate-clock";
    975		clocks = <&func_48m_ck>;
    976		ti,bit-shift = <22>;
    977		reg = <0x0200>;
    978	};
    979
    980	uart3_ick: uart3_ick@214 {
    981		#clock-cells = <0>;
    982		compatible = "ti,omap3-interface-clock";
    983		clocks = <&l4_ck>;
    984		ti,bit-shift = <2>;
    985		reg = <0x0214>;
    986	};
    987
    988	uart3_fck: uart3_fck@204 {
    989		#clock-cells = <0>;
    990		compatible = "ti,wait-gate-clock";
    991		clocks = <&func_48m_ck>;
    992		ti,bit-shift = <2>;
    993		reg = <0x0204>;
    994	};
    995
    996	gpios_ick: gpios_ick@410 {
    997		#clock-cells = <0>;
    998		compatible = "ti,omap3-interface-clock";
    999		clocks = <&sys_ck>;
   1000		ti,bit-shift = <2>;
   1001		reg = <0x0410>;
   1002	};
   1003
   1004	gpios_fck: gpios_fck@400 {
   1005		#clock-cells = <0>;
   1006		compatible = "ti,wait-gate-clock";
   1007		clocks = <&func_32k_ck>;
   1008		ti,bit-shift = <2>;
   1009		reg = <0x0400>;
   1010	};
   1011
   1012	mpu_wdt_ick: mpu_wdt_ick@410 {
   1013		#clock-cells = <0>;
   1014		compatible = "ti,omap3-interface-clock";
   1015		clocks = <&sys_ck>;
   1016		ti,bit-shift = <3>;
   1017		reg = <0x0410>;
   1018	};
   1019
   1020	mpu_wdt_fck: mpu_wdt_fck@400 {
   1021		#clock-cells = <0>;
   1022		compatible = "ti,wait-gate-clock";
   1023		clocks = <&func_32k_ck>;
   1024		ti,bit-shift = <3>;
   1025		reg = <0x0400>;
   1026	};
   1027
   1028	sync_32k_ick: sync_32k_ick@410 {
   1029		#clock-cells = <0>;
   1030		compatible = "ti,omap3-interface-clock";
   1031		clocks = <&sys_ck>;
   1032		ti,bit-shift = <1>;
   1033		reg = <0x0410>;
   1034	};
   1035
   1036	wdt1_ick: wdt1_ick@410 {
   1037		#clock-cells = <0>;
   1038		compatible = "ti,omap3-interface-clock";
   1039		clocks = <&sys_ck>;
   1040		ti,bit-shift = <4>;
   1041		reg = <0x0410>;
   1042	};
   1043
   1044	omapctrl_ick: omapctrl_ick@410 {
   1045		#clock-cells = <0>;
   1046		compatible = "ti,omap3-interface-clock";
   1047		clocks = <&sys_ck>;
   1048		ti,bit-shift = <5>;
   1049		reg = <0x0410>;
   1050	};
   1051
   1052	cam_fck: cam_fck@200 {
   1053		#clock-cells = <0>;
   1054		compatible = "ti,gate-clock";
   1055		clocks = <&func_96m_ck>;
   1056		ti,bit-shift = <31>;
   1057		reg = <0x0200>;
   1058	};
   1059
   1060	cam_ick: cam_ick@210 {
   1061		#clock-cells = <0>;
   1062		compatible = "ti,omap3-no-wait-interface-clock";
   1063		clocks = <&l4_ck>;
   1064		ti,bit-shift = <31>;
   1065		reg = <0x0210>;
   1066	};
   1067
   1068	mailboxes_ick: mailboxes_ick@210 {
   1069		#clock-cells = <0>;
   1070		compatible = "ti,omap3-interface-clock";
   1071		clocks = <&l4_ck>;
   1072		ti,bit-shift = <30>;
   1073		reg = <0x0210>;
   1074	};
   1075
   1076	wdt4_ick: wdt4_ick@210 {
   1077		#clock-cells = <0>;
   1078		compatible = "ti,omap3-interface-clock";
   1079		clocks = <&l4_ck>;
   1080		ti,bit-shift = <29>;
   1081		reg = <0x0210>;
   1082	};
   1083
   1084	wdt4_fck: wdt4_fck@200 {
   1085		#clock-cells = <0>;
   1086		compatible = "ti,wait-gate-clock";
   1087		clocks = <&func_32k_ck>;
   1088		ti,bit-shift = <29>;
   1089		reg = <0x0200>;
   1090	};
   1091
   1092	mspro_ick: mspro_ick@210 {
   1093		#clock-cells = <0>;
   1094		compatible = "ti,omap3-interface-clock";
   1095		clocks = <&l4_ck>;
   1096		ti,bit-shift = <27>;
   1097		reg = <0x0210>;
   1098	};
   1099
   1100	mspro_fck: mspro_fck@200 {
   1101		#clock-cells = <0>;
   1102		compatible = "ti,wait-gate-clock";
   1103		clocks = <&func_96m_ck>;
   1104		ti,bit-shift = <27>;
   1105		reg = <0x0200>;
   1106	};
   1107
   1108	fac_ick: fac_ick@210 {
   1109		#clock-cells = <0>;
   1110		compatible = "ti,omap3-interface-clock";
   1111		clocks = <&l4_ck>;
   1112		ti,bit-shift = <25>;
   1113		reg = <0x0210>;
   1114	};
   1115
   1116	fac_fck: fac_fck@200 {
   1117		#clock-cells = <0>;
   1118		compatible = "ti,wait-gate-clock";
   1119		clocks = <&func_12m_ck>;
   1120		ti,bit-shift = <25>;
   1121		reg = <0x0200>;
   1122	};
   1123
   1124	hdq_ick: hdq_ick@210 {
   1125		#clock-cells = <0>;
   1126		compatible = "ti,omap3-interface-clock";
   1127		clocks = <&l4_ck>;
   1128		ti,bit-shift = <23>;
   1129		reg = <0x0210>;
   1130	};
   1131
   1132	hdq_fck: hdq_fck@200 {
   1133		#clock-cells = <0>;
   1134		compatible = "ti,wait-gate-clock";
   1135		clocks = <&func_12m_ck>;
   1136		ti,bit-shift = <23>;
   1137		reg = <0x0200>;
   1138	};
   1139
   1140	i2c1_ick: i2c1_ick@210 {
   1141		#clock-cells = <0>;
   1142		compatible = "ti,omap3-interface-clock";
   1143		clocks = <&l4_ck>;
   1144		ti,bit-shift = <19>;
   1145		reg = <0x0210>;
   1146	};
   1147
   1148	i2c2_ick: i2c2_ick@210 {
   1149		#clock-cells = <0>;
   1150		compatible = "ti,omap3-interface-clock";
   1151		clocks = <&l4_ck>;
   1152		ti,bit-shift = <20>;
   1153		reg = <0x0210>;
   1154	};
   1155
   1156	gpmc_fck: gpmc_fck@238 {
   1157		#clock-cells = <0>;
   1158		compatible = "ti,fixed-factor-clock";
   1159		clocks = <&core_l3_ck>;
   1160		ti,clock-div = <1>;
   1161		ti,autoidle-shift = <1>;
   1162		reg = <0x0238>;
   1163		ti,clock-mult = <1>;
   1164	};
   1165
   1166	sdma_fck: sdma_fck {
   1167		#clock-cells = <0>;
   1168		compatible = "fixed-factor-clock";
   1169		clocks = <&core_l3_ck>;
   1170		clock-mult = <1>;
   1171		clock-div = <1>;
   1172	};
   1173
   1174	sdma_ick: sdma_ick@238 {
   1175		#clock-cells = <0>;
   1176		compatible = "ti,fixed-factor-clock";
   1177		clocks = <&core_l3_ck>;
   1178		ti,clock-div = <1>;
   1179		ti,autoidle-shift = <0>;
   1180		reg = <0x0238>;
   1181		ti,clock-mult = <1>;
   1182	};
   1183
   1184	sdrc_ick: sdrc_ick@238 {
   1185		#clock-cells = <0>;
   1186		compatible = "ti,fixed-factor-clock";
   1187		clocks = <&core_l3_ck>;
   1188		ti,clock-div = <1>;
   1189		ti,autoidle-shift = <2>;
   1190		reg = <0x0238>;
   1191		ti,clock-mult = <1>;
   1192	};
   1193
   1194	des_ick: des_ick@21c {
   1195		#clock-cells = <0>;
   1196		compatible = "ti,omap3-interface-clock";
   1197		clocks = <&l4_ck>;
   1198		ti,bit-shift = <0>;
   1199		reg = <0x021c>;
   1200	};
   1201
   1202	sha_ick: sha_ick@21c {
   1203		#clock-cells = <0>;
   1204		compatible = "ti,omap3-interface-clock";
   1205		clocks = <&l4_ck>;
   1206		ti,bit-shift = <1>;
   1207		reg = <0x021c>;
   1208	};
   1209
   1210	rng_ick: rng_ick@21c {
   1211		#clock-cells = <0>;
   1212		compatible = "ti,omap3-interface-clock";
   1213		clocks = <&l4_ck>;
   1214		ti,bit-shift = <2>;
   1215		reg = <0x021c>;
   1216	};
   1217
   1218	aes_ick: aes_ick@21c {
   1219		#clock-cells = <0>;
   1220		compatible = "ti,omap3-interface-clock";
   1221		clocks = <&l4_ck>;
   1222		ti,bit-shift = <3>;
   1223		reg = <0x021c>;
   1224	};
   1225
   1226	pka_ick: pka_ick@21c {
   1227		#clock-cells = <0>;
   1228		compatible = "ti,omap3-interface-clock";
   1229		clocks = <&l4_ck>;
   1230		ti,bit-shift = <4>;
   1231		reg = <0x021c>;
   1232	};
   1233
   1234	usb_fck: usb_fck@204 {
   1235		#clock-cells = <0>;
   1236		compatible = "ti,wait-gate-clock";
   1237		clocks = <&func_48m_ck>;
   1238		ti,bit-shift = <0>;
   1239		reg = <0x0204>;
   1240	};
   1241};