cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

omap3-gta04a5one.dts (3150B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
      4 */
      5
      6#include "omap3-gta04a5.dts"
      7
      8&omap3_pmx_core {
      9	model = "Goldelico GTA04A5/Letux 2804 with OneNAND";
     10
     11	gpmc_pins: pinmux_gpmc_pins {
     12		pinctrl-single,pins = <
     13
     14			/* address lines */
     15			OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
     16			OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
     17			OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
     18
     19			/* data lines, gpmc_d0..d7 not muxable according to TRM */
     20			OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
     21			OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
     22			OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
     23			OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
     24			OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */
     25			OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0)        /* gpmc_d13.gpmc_d13 */
     26			OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0)        /* gpmc_d14.gpmc_d14 */
     27			OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0)        /* gpmc_d15.gpmc_d15 */
     28
     29			/*
     30			 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
     31			 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
     32			 */
     33			OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
     34			OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
     35		>;
     36	};
     37};
     38
     39&gpmc {
     40	/* switch inherited setup to OneNAND */
     41
     42	ranges = <0 0 0x04000000 0x1000000>;	/* CS0: 16MB for OneNAND */
     43	pinctrl-names = "default";
     44	pinctrl-0 = <&gpmc_pins>;
     45
     46	/delete-node/ nand@0,0;
     47
     48	onenand@0,0 {
     49
     50		#address-cells = <1>;
     51		#size-cells = <1>;
     52		compatible = "ti,omap2-onenand";
     53		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
     54
     55		gpmc,sync-read;
     56		gpmc,sync-write;
     57		gpmc,burst-length = <16>;
     58		gpmc,burst-read;
     59		gpmc,burst-wrap;
     60		gpmc,burst-write;
     61		gpmc,device-width = <2>;
     62		gpmc,mux-add-data = <2>;
     63		gpmc,cs-on-ns = <0>;
     64		gpmc,cs-rd-off-ns = <87>;
     65		gpmc,cs-wr-off-ns = <87>;
     66		gpmc,adv-on-ns = <0>;
     67		gpmc,adv-rd-off-ns = <10>;
     68		gpmc,adv-wr-off-ns = <10>;
     69		gpmc,oe-on-ns = <15>;
     70		gpmc,oe-off-ns = <87>;
     71		gpmc,we-on-ns = <0>;
     72		gpmc,we-off-ns = <87>;
     73		gpmc,rd-cycle-ns = <112>;
     74		gpmc,wr-cycle-ns = <112>;
     75		gpmc,access-ns = <81>;
     76		gpmc,page-burst-access-ns = <15>;
     77		gpmc,bus-turnaround-ns = <0>;
     78		gpmc,cycle2cycle-delay-ns = <0>;
     79		gpmc,wait-monitoring-ns = <0>;
     80		gpmc,clk-activation-ns = <5>;
     81		gpmc,wr-data-mux-bus-ns = <30>;
     82		gpmc,wr-access-ns = <81>;
     83		gpmc,sync-clk-ps = <15000>;
     84
     85		x-loader@0 {
     86			label = "X-Loader";
     87			reg = <0 0x80000>;
     88		};
     89
     90		bootloaders@80000 {
     91			label = "U-Boot";
     92			reg = <0x80000 0x1c0000>;
     93		};
     94
     95		bootloaders_env@240000 {
     96			label = "U-Boot Env";
     97			reg = <0x240000 0x40000>;
     98		};
     99
    100		kernel@280000 {
    101			label = "Kernel";
    102			reg = <0x280000 0x600000>;
    103		};
    104
    105		filesystem@880000 {
    106			label = "File System";
    107			reg = <0x880000 0>;	/* 0 = MTDPART_SIZ_FULL */
    108		};
    109
    110	};
    111};