cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap3-ha-common.dtsi (2323B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      4 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
      5 */
      6
      7#include "omap3-tao3530.dtsi"
      8
      9/ {
     10	gpio_poweroff {
     11		pinctrl-names = "default";
     12		pinctrl-0 = <&poweroff_pins>;
     13
     14		compatible = "gpio-poweroff";
     15		gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;	/* GPIO 168 */
     16	};
     17};
     18
     19&omap3_pmx_core {
     20	sound2_pins: pinmux_sound2_pins {
     21		pinctrl-single,pins = <
     22			OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4)	/* gpmc_d8 gpio_44 */
     23		>;
     24	};
     25
     26	led_blue_pins: pinmux_led_blue_pins {
     27		pinctrl-single,pins = <
     28			OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4)	/* cam_xclka gpio_96, LED blue */
     29		>;
     30	};
     31
     32	led_green_pins: pinmux_led_green_pins {
     33		pinctrl-single,pins = <
     34			OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4)	/* cam_d8 gpio_107, LED green */
     35		>;
     36	};
     37
     38	led_red_pins: pinmux_led_red_pins {
     39		pinctrl-single,pins = <
     40			OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* cam_xclkb gpio_111, LED red */
     41		>;
     42	};
     43
     44	poweroff_pins: pinmux_poweroff_pins {
     45		pinctrl-single,pins = <
     46			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* i2c2_scl gpio_168 */
     47		>;
     48	};
     49
     50	powerdown_input_pins: pinmux_powerdown_input_pins {
     51		pinctrl-single,pins = <
     52			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4)	/* i2c2_sda gpio_183 */
     53		>;
     54	};
     55
     56	fpga_boot0_pins: fpga_boot0_pins {
     57		pinctrl-single,pins = <
     58			OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4)	/* cam_d2 gpio_101 */
     59			OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4)	/* cam_d3 gpio_102 */
     60			OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4)	/* cam_d4 gpio_103 */
     61			OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_d5 gpio_104 */
     62		>;
     63	};
     64
     65	fpga_boot1_pins: fpga_boot1_pins {
     66		pinctrl-single,pins = <
     67			OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4)	/* gpmc_d10 gpio_46 */
     68			OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4)	/* gpmc_d11 gpio_47 */
     69			OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4)	/* gpmc_d12 gpio_48 */
     70			OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4)	/* gpmc_d13 gpio_49 */
     71		>;
     72	};
     73};
     74
     75/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
     76&i2c2 {
     77	status = "disabled";
     78};
     79
     80&i2c3 {
     81	clock-frequency = <100000>;
     82
     83	pinctrl-names = "default";
     84	pinctrl-0 = <&i2c3_pins>;
     85};