omap3-zoom3.dts (6682B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "omap36xx.dtsi" 8#include "omap-zoom-common.dtsi" 9 10/ { 11 model = "TI Zoom3"; 12 compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3"; 13 14 cpus { 15 cpu@0 { 16 cpu0-supply = <&vcc>; 17 }; 18 }; 19 20 memory@80000000 { 21 device_type = "memory"; 22 reg = <0x80000000 0x20000000>; /* 512 MB */ 23 }; 24 25 vddvario: regulator-vddvario { 26 compatible = "regulator-fixed"; 27 regulator-name = "vddvario"; 28 regulator-always-on; 29 }; 30 31 vdd33a: regulator-vdd33a { 32 compatible = "regulator-fixed"; 33 regulator-name = "vdd33a"; 34 regulator-always-on; 35 }; 36 37 wl12xx_vmmc: wl12xx_vmmc { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&wl12xx_gpio>; 40 compatible = "regulator-fixed"; 41 regulator-name = "vwl1271"; 42 regulator-min-microvolt = <1800000>; 43 regulator-max-microvolt = <1800000>; 44 gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ 45 startup-delay-us = <70000>; 46 enable-active-high; 47 }; 48}; 49 50&omap3_pmx_core { 51 /* REVISIT: twl gpio0 is mmc0_cd */ 52 mmc1_pins: pinmux_mmc1_pins { 53 pinctrl-single,pins = < 54 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 55 OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 56 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 57 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 58 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 59 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 60 >; 61 }; 62 63 mmc2_pins: pinmux_mmc2_pins { 64 pinctrl-single,pins = < 65 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 66 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 67 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 68 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 69 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 70 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 71 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ 72 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ 73 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ 74 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ 75 >; 76 }; 77 78 mmc3_pins: pinmux_mmc3_pins { 79 pinctrl-single,pins = < 80 OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ 81 OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ 82 >; 83 }; 84 85 uart1_pins: pinmux_uart1_pins { 86 pinctrl-single,pins = < 87 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ 88 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ 89 OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 90 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 91 >; 92 }; 93 94 uart2_pins: pinmux_uart2_pins { 95 pinctrl-single,pins = < 96 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 97 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 98 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 99 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 100 >; 101 }; 102 103 uart3_pins: pinmux_uart3_pins { 104 pinctrl-single,pins = < 105 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 106 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 107 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 108 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 109 >; 110 }; 111 112 /* wl12xx GPIO output for WLAN_EN */ 113 wl12xx_gpio: pinmux_wl12xx_gpio { 114 pinctrl-single,pins = < 115 OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ 116 >; 117 }; 118}; 119 120&omap3_pmx_core2 { 121 mmc3_2_pins: pinmux_mmc3_2_pins { 122 pinctrl-single,pins = < 123 OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ 124 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ 125 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 126 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ 127 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ 128 >; 129 }; 130}; 131 132&omap3_pmx_wkup { 133 wlan_host_wkup: pinmux_wlan_host_wkup_pins { 134 pinctrl-single,pins = < 135 OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ 136 >; 137 }; 138}; 139 140&i2c1 { 141 clock-frequency = <2600000>; 142 143 twl: twl@48 { 144 reg = <0x48>; 145 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 146 interrupt-parent = <&intc>; 147 }; 148}; 149 150#include "twl4030.dtsi" 151 152&i2c2 { 153 clock-frequency = <400000>; 154}; 155 156&i2c3 { 157 clock-frequency = <400000>; 158 159 /* 160 * TVP5146 Video decoder-in for analog input support. 161 */ 162 tvp5146@5c { 163 compatible = "ti,tvp5146m2"; 164 reg = <0x5c>; 165 }; 166}; 167 168&twl_gpio { 169 ti,use-leds; 170}; 171 172&mmc1 { 173 vmmc-supply = <&vmmc1>; 174 vqmmc-supply = <&vsim>; 175 bus-width = <4>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&mmc1_pins>; 178}; 179/* 180&mmc2 { 181 vmmc-supply = <&vmmc2>; 182 ti,non-removable; 183 bus-width = <8>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&mmc2_pins>; 186}; 187*/ 188&mmc3 { 189 vmmc-supply = <&wl12xx_vmmc>; 190 non-removable; 191 bus-width = <4>; 192 cap-power-off-card; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; 195 196 #address-cells = <1>; 197 #size-cells = <0>; 198 wlcore: wlcore@2 { 199 compatible = "ti,wl1271"; 200 reg = <2>; 201 interrupt-parent = <&gpio6>; 202 interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ 203 ref-clock-frequency = <26000000>; 204 }; 205}; 206 207&uart1 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&uart1_pins>; 210}; 211 212&uart2 { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&uart2_pins>; 215}; 216 217&uart3 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&uart3_pins>; 220}; 221 222&uart4 { 223 status = "disabled"; 224}; 225 226&usb_otg_hs { 227 interface-type = <0>; 228 usb-phy = <&usb2_phy>; 229 mode = <3>; 230 power = <50>; 231};