cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap36xx-clocks.dtsi (2524B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Device Tree Source for OMAP36xx clock data
      4 *
      5 * Copyright (C) 2013 Texas Instruments, Inc.
      6 */
      7&cm_clocks {
      8	dpll4_ck: dpll4_ck@d00 {
      9		#clock-cells = <0>;
     10		compatible = "ti,omap3-dpll-per-j-type-clock";
     11		clocks = <&sys_ck>, <&sys_ck>;
     12		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
     13	};
     14
     15	dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
     16		#clock-cells = <0>;
     17		compatible = "ti,hsdiv-gate-clock";
     18		clocks = <&dpll4_m5x2_mul_ck>;
     19		ti,bit-shift = <0x1e>;
     20		reg = <0x0d00>;
     21		ti,set-rate-parent;
     22		ti,set-bit-to-disable;
     23	};
     24
     25	dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
     26		#clock-cells = <0>;
     27		compatible = "ti,hsdiv-gate-clock";
     28		clocks = <&dpll4_m2x2_mul_ck>;
     29		ti,bit-shift = <0x1b>;
     30		reg = <0x0d00>;
     31		ti,set-bit-to-disable;
     32	};
     33
     34	dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
     35		#clock-cells = <0>;
     36		compatible = "ti,hsdiv-gate-clock";
     37		clocks = <&dpll3_m3x2_mul_ck>;
     38		ti,bit-shift = <0xc>;
     39		reg = <0x0d00>;
     40		ti,set-bit-to-disable;
     41	};
     42
     43	dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
     44		#clock-cells = <0>;
     45		compatible = "ti,hsdiv-gate-clock";
     46		clocks = <&dpll4_m3x2_mul_ck>;
     47		ti,bit-shift = <0x1c>;
     48		reg = <0x0d00>;
     49		ti,set-bit-to-disable;
     50	};
     51
     52	dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
     53		#clock-cells = <0>;
     54		compatible = "ti,hsdiv-gate-clock";
     55		clocks = <&dpll4_m6x2_mul_ck>;
     56		ti,bit-shift = <0x1f>;
     57		reg = <0x0d00>;
     58		ti,set-bit-to-disable;
     59	};
     60
     61	clock@1000 {
     62		compatible = "ti,clksel";
     63		reg = <0x1000>;
     64		#clock-cells = <2>;
     65		#address-cells = <0>;
     66
     67		uart4_fck: clock-uart4-fck {
     68			#clock-cells = <0>;
     69			compatible = "ti,wait-gate-clock";
     70			clock-output-names = "uart4_fck";
     71			clocks = <&per_48m_fck>;
     72			ti,bit-shift = <18>;
     73		};
     74	};
     75};
     76
     77&dpll4_m2x2_mul_ck {
     78	clock-mult = <1>;
     79};
     80
     81&dpll4_m3x2_mul_ck {
     82	clock-mult = <1>;
     83};
     84
     85&dpll4_m4x2_mul_ck {
     86	ti,clock-mult = <1>;
     87};
     88
     89&dpll4_m5x2_mul_ck {
     90	ti,clock-mult = <1>;
     91};
     92
     93&dpll4_m6x2_mul_ck {
     94	clock-mult = <1>;
     95};
     96
     97&cm_clockdomains {
     98	dpll4_clkdm: dpll4_clkdm {
     99		compatible = "ti,clockdomain";
    100		clocks = <&dpll4_ck>;
    101	};
    102
    103	per_clkdm: per_clkdm {
    104		compatible = "ti,clockdomain";
    105		clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
    106			 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
    107			 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
    108			 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
    109			 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
    110			 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
    111			 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
    112			 <&mcbsp4_ick>, <&uart4_fck>;
    113	};
    114};
    115
    116&dpll4_m4_ck {
    117	ti,max-div = <31>;
    118};